搜索：viterbi - 虫虫下载站

嵌入式/单片机编程  一种基于FPGA的Viterbi译码器一种基于FPGA的Viterbi译码器

一种基于FPGA的Viterbi译码器一种基于FPGA的Viterbi译码器

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matlab例程  it is a matlab program that describes DVB-S channel and simulation of Viterbi decoding

it is a matlab program that describes DVB-S channel and simulation of Viterbi decoding

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通讯/手机编程  The Viterbi algorithm

The Viterbi algorithm

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数学计算  viterbi algorithm_code_verilog

viterbi algorithm_code_verilog

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VC书籍  Hard Viterbi QPSK in AWGN, Rayleight soft Viterbi QAM in AWGN, Rayleight viterbi QAM in AWGN, Rayl

Hard Viterbi QPSK in AWGN, Rayleight soft Viterbi QAM in AWGN, Rayleight viterbi QAM in AWGN, Rayleight viterbi QPSK in AWGN, Rayleight

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JavaScript Viterbi in java. ViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterb

Viterbi in java. ViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbiViterbi

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其他  FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation

FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation

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通讯/手机编程  It is turbo encoder and decoder qritten for communication module has viterbi

It is turbo encoder and decoder qritten for communication module has viterbi

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源码  基于FPGA的viterbi设计及Verilog代码

viterbi译码算法是一种卷积码的解码算法。优点不说了。缺点就是随着约束长度的增加算法的复杂度增加很快。约束长度N为7时要比较的路径就有64条，为8时路径变为128条。 (2<<(N-1))。所以viterbi译码一般应用在约束长度小于10的场合中。先说编码（举例约束长度为7）：编码器7个延迟器的状态（0，1）组成了整个编码器的64个状 ...

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源码  Verilog源代码关于viterbi设计

&nbsp;(n, k, N)卷积码的状态数为2k (N−1) ，对每一时刻要做2k (N−1) 次“加－比－存”操作，每一操作包括2k 次加法和2k −1 次比较，同时要保留2k (N−1) 条幸存路径。由此可见，Viterbi 算法的复杂度与信道质量无关，其计算量和存储量都随约束长度N 和信息元分组k 呈指数增长。因此，在约束长度和信息元分 ...

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