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Modem编程 Make and answer phone calls Detect tone and pulse digit from the phone line Capture Caller ID
Make and answer phone calls
Detect tone and pulse digit from the phone line
Capture Caller ID
Support blind transfer, single-step transfer/conference, consultation transfer/conference, hold, unhold.
Control of the local phone handset, microphone and speaker of the modem
Send and receive fa ...
系统设计方案 This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency
detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise reduction whe ...
VHDL/FPGA/Verilog This file contains a selection of VHDL source files which serve to illustrate the diversity and powe
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp
terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. ...
DSP编程 FIR滤波器的C++实现 Below are program source listings for FIR.h and FIR.cpp, the header file and class fil
FIR滤波器的C++实现
Below are program source listings for FIR.h and FIR.cpp, the header file and class file for implementing arbitrary causal FIR filters in the Synthesis Tool Kit (STK) framework
通讯编程文档 With the advent of multimedia, digital signal processing (DSP) of sound has emerged from the shadow
With the advent of multimedia, digital signal processing (DSP) of sound has emerged from the shadow of bandwidth-limited speech processing. Today, the main appli- cations of audio DSP are high quality audio coding and the digital generation and manipulation of music signals. They share common resear ...
VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码
DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...
BREW编程 ECE345, Visual-to-Audio Electronic Travel Aid Code for TM320C54x (v2a.asm) download This project
ECE345, Visual-to-Audio Electronic Travel Aid
Code for TM320C54x (v2a.asm) download
This project involves the design and implementation of a audio synthesis device that converts moving images into audio signals. The system is built on a TM320C54x DSP with interface to an IMAQ camera module via the ...
单片机开发 8051单片机源码verilog版本 包括rtl
8051单片机源码verilog版本
包括rtl， testbench， synthesis
VHDL/FPGA/Verilog 1. Learn the basic constructs of VHDL 2. Learn the modeling structure of VHDL 3. Understand the de
1. Learn the basic constructs of VHDL
2. Learn the modeling structure of VHDL
3. Understand the design environments
– Simulation
– Synthesis
VHDL/FPGA/Verilog The xapp851.zip archive includes the following subdirectories. The specific contents of each subdi
The xapp851.zip archive includes the following subdirectories. The specific
contents of each subdirectory below:
\rtl - HDL design files
\sim - simulation files
\synth - Synthesis related files
\par - Place/Route related files