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VHDL/FPGA/Verilog This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPG
This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
matlab例程 本函数在matlab实现阻抗圆图
本函数在matlab实现阻抗圆图，通过调用switch（）函数，可以得出传输线的反射系数，以及支节匹配等参数，本函数可以实现单、双和三支节匹配。
DSP编程 This program requires the DSP2833x header files. // // This program requires an external I2C RT
This program requires the DSP2833x header files.
//
// This program requires an external I2C RTC connected to
// the I2C bus at address 0x6f.
//
// As supplied, this project is configured for "boot to SARAM"
// operation. The 2833x Boot Mode table is shown below.
// For information o ...
DSP编程 This program requires the DSP2833x header files. // // As supplied, this project is configured
This program requires the DSP2833x header files.
//
// As supplied, this project is configured for "boot to SARAM"
// operation. The 2833x Boot Mode table is shown below.
// For information on configuring the boot mode of an eZdsp,
// please refer to the documentation included with the ...
系统设计方案 此题目是通过键盘来实现密码输入是否正确
此题目是通过键盘来实现密码输入是否正确，正确的时候数码管亮，否则发出报警声。
判断是按键还是干扰是非常有用的，它体现了一个系统的抗干扰能力。高低电平在瞬间的变换是很正常的，如果没有这条语句，系统很容易出错。
其中2秒是由定时器0来完成的。
在程序的定时器中断中，用switch代替了if else结构，使得程序的可读 ...
单片机开发 This software is developed to provide ease with controller design. For PID control, options are give
This software is developed to provide ease with controller design. For PID control, options are given
to design and analyse the compensated and uncompensated system. You are free to choice among Proportional
PI, PD and PID mode of control. Both frequency and time domain characteristics can be ob ...
VHDL/FPGA/Verilog RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the
RS_latch using vhdl,
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q.
Normally, in stor ...
DSP编程 hese are the zip files that are associated with application note ADSP-BF533 Blackfin Booting Pro
hese are the zip files that are associated with application note
ADSP-BF533 Blackfin Booting Process (EE-240)
example.zip:
Used throughout the EE-note to explain in detail the various booting modes.
BF533 Ez Kit Multiple DXE Boot.zip:
Multi-DXE Boot Example used with the ADSP-BF533 Ez-Kit Lit ...
matlab例程 视频质料 在matlab环境中如何使用radiobutton
视频质料 在matlab环境中如何使用radiobutton，switch语句，边缘检测