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matlab例程 This demo develops the steady-state characteristics of an induction motor First start the simulation
This demo develops the steady-state characteristics of an induction motor First start the simulation, then Double click the <PLOTS> block to view torque-speed and
current-speed curves and the current circle diagram
数值算法/人工智能 this program solves the steady-state navier-stokes eqn in 2d for the flow in a driven cavity problem
this program solves the steady-state navier-stokes eqn in 2d for the flow in a driven cavity problem.
the function solved for is the streamfunction.
the velocity may be obtained by differentiating
the streamfunction.
文件格式 An adaptive fuzzy integral sliding mode controller for mismatched time-varying linear systems is p
An adaptive fuzzy integral sliding mode
controller for mismatched time-varying linear systems is
presented in this paper. The proposed fuzzy integral sliding
mode controller is designed to have zero steady state
system error under step inputs and alleviate the undesired
chattering around the sliding ...
书籍 Power System Stability Modelling
Modern day large power systems are essentially dynamic systems with stringent
requirements of high reliability for the continuous availability of electricity.
Reliability is contingent on the power system retaining stable operation during
steady-state operation and also following disturbances. The s ...
书籍 Switching+Systems+by+Invariance+Analysis1
Switched systems are embedded devices widespread in industrial
applications such as power electronics and automotive control. They
consist of continuous-time dynamical subsystems and a rule that
controls the switching between them. Under a suitable control rule, the
system can improve its steady-sta ...
allegro State Machine Coding Styles for Synthesis
&nbsp;
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson&#39;s 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve&#39;s paper alsooffers in-depth background concernin ...
Mentor Design Safe Verilog State Machine(Synplicity)
&nbsp;
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...
Mentor Creating Safe State Machines(Mentor)
&nbsp;
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptabl ...
可编程逻辑 State Machine Coding Styles for Synthesis
&nbsp;
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson&#39;s 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve&#39;s paper alsooffers in-depth background concernin ...
可编程逻辑 Design Safe Verilog State Machine(Synplicity)
&nbsp;
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...