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matlab例程 In engineering, compensation is planning for side effects or other unintended issues in a design. Th
In engineering, compensation is planning for side effects or other unintended issues in a design. The design of an invention can itself also be to compensate for some other existing issue or exception.
One example is in a voltage-controlled crystal oscillator (VCXO), which is normally affected not ...
VHDL/FPGA/Verilog This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with inte
This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switches on the red LEDs. The &#64257 rst program uses the programmed I/O approach a ...
嵌入式/单片机编程 The objective is to set up SPI communication between VTI Technologies digital pressure sensor comp
The objective is to set up SPI communication between VTI Technologies digital pressure sensor
component and an MCU of an application device ATMEGA16L. In this code example:
?The MCU is configured
?SCP1000-D01 is initialized and configured
?The high resolution measurement mode is activated
?Temperat ...
VHDL/FPGA/Verilog The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. I
The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to implement the digital DC/DC Converters have been rese ...
VHDL/FPGA/Verilog In this paper, a new method is introduced to implement chaotic generators based on the Henon map and
In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is ...
VHDL/FPGA/Verilog RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the
RS_latch using vhdl,
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q.
Normally, in stor ...
加密解密 The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at
The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. This contribution attempts to provide a state-of-the-art description of this topic. First, the advantages of reconfi ...
其他 AVR single-chip developed by a very low threshold, as long as the computer will be able to study the
AVR single-chip developed by a very low threshold, as long as the computer will be able to study the development of AVR microcontroller. Only a single-chip ISP download beginners line, the editing, debugging of software programs through a direct line into the AVR microcontroller, which can develop A ...
单片机开发 AVR single-chip developed by a very low threshold, as long as the computer will be able to study the
AVR single-chip developed by a very low threshold, as long as the computer will be able to study the development of AVR microcontroller. Only a single-chip ISP download beginners line, the editing, debugging of software programs through a direct line into the AVR microcontroller, which can develop A ...
C/C++语言编程 文件Java排课系统的报告
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