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电源技术 LTC4099 USB电源管理和电池充电
 
The LTC®4099 high effi ciency USB power manager andLi-Ion/Polymer battery charger seamlessly managespower distribution from multiple sources in portableapplications. It is differentiated from other USB powermanagers by its bidirectional I2C port that allows the hostmicroprocessor to c ...
单片机编程 基于双ATmega128的安检力学试验机设计
针对当前安检力学试验机所能完成的试验种类单一、自动化程度低等问题，提出一种以ATmega128单片机为核心控制器的安检力学试验机的设计。详细阐述了该安检力学试验机各个组成部分的设计原理和方案，并且给出了各部分的软件设计思想和操作流程。经过大量测试试验表明：设计的安检力学试验机可以完成多达十余种的力学安检试验 ...
教程资料 CPLD和FPGA设计介绍
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system ...
通信网络 MEMS 经典教材
The field of microelectromechanical systems (MEMS), particularly micromachinedmechanical transducers, has been expanding over recent years, and the productioncosts of these devices continue to fall. Using materials, fabrication processes, anddesign tools originally developed for the microelectronic ...
传感与控制 MEMS惯性传感器的焊接指南
Abstract: Standard PCB design and mounting processes can adversely influence MEMS inertial sensors.This application note contains guidelines for the layout, soldering, and mounting of MEMS inertialsensors in LGA packages in order to reduce stresses and improve functionality.
开发工具 如何仿真IP核(建立modelsim仿真库完整解析)
IP核生成文件：（Xilinx/Altera 同）
IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则asyn_fifo.veo 给出了例化该核方式（或者在 Edit－》Language Template-》COREGEN 中找到verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块 ...
可编程逻辑 CPLD和FPGA设计介绍
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system ...
仿真技术 如何仿真IP核(建立modelsim仿真库完整解析)
IP核生成文件：（Xilinx/Altera 同）
IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则asyn_fifo.veo 给出了例化该核方式（或者在 Edit－》Language Template-》COREGEN 中找到verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块 ...
通讯/手机编程 This module can be used to interface to the MMC card in MMC or * SPI modes. It supports a multiple
This module can be used to interface to the MMC card in MMC or
* SPI modes. It supports a multiple card environment. The reset and
* identification processes assume multiple cards on the bus.
* In MMC mode, the card number is used as the RCA operand in the
* commands.
其他嵌入式/单片机内容 Support is available from MIPS Technologies Inc. - problems should be addressed to support@mips.co
Support is available from MIPS Technologies Inc. - problems should be
addressed to support@mips.com。This product may be controlled for export purposes.
You may not export, or transfer for the purpose of reexport, any technical
data received hereunder or the product produced by use of such techni ...