搜索结果

找到约 196 项符合 phase-lockedmloop 的查询结果

系统设计方案 A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer

A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, w ...
https://www.eeworm.com/dl/678/283593.html
下载: 193
查看: 1071

系统设计方案 Fast settling-time added to the already conflicting requirements of narrow channel spacing and low

Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator ...
https://www.eeworm.com/dl/678/283596.html
下载: 142
查看: 1055

matlab例程 %%% Demos for PUMA algorithms %%% We present four matlab demos for PUMA. demo1, demo2, demo3, and

%%% Demos for PUMA algorithms %%% We present four matlab demos for PUMA. demo1, demo2, demo3, and demo4 illustrate PUMA working with different parameters and with four different images. All you need to do is to run each of the demos. Please be sure that all the files are put on an accessibl ...
https://www.eeworm.com/dl/665/287260.html
下载: 49
查看: 1058

行业发展研究 无线传感器网络的主要功能是实现数据发布,在接收到信息查询时能够以有效的方式传输给查询者.目前的数据发布方式通常基于洪泛机制查询信息,浪费了有限的能源.虽然一些最近的数据发布协议从不同程度上解决了这一问

无线传感器网络的主要功能是实现数据发布,在接收到信息查询时能够以有效的方式传输给查询者.目前的数据发布方式通常基于洪泛机制查询信息,浪费了有限的能源.虽然一些最近的数据发布协议从不同程度上解决了这一问题,但不能保证查询成功率.基于圆形节点分布网络模型提出了一种既能减少能源消耗,又能提高成功率的数据发布模式 ...
https://www.eeworm.com/dl/692/289671.html
下载: 38
查看: 1076

单片机开发 A major goal of this book is to show to make devices that are inherently reliable by design. While a

A major goal of this book is to show to make devices that are inherently reliable by design. While a lot of attention has been given to “quality improvement,” the majority of the emphasis has been placed on the processes that occur after the design of a product is complete. Design deficiencies are ...
https://www.eeworm.com/dl/648/326591.html
下载: 72
查看: 1076

其他书籍 UML指南An important part of the Unified Modeling Language (UML) is the facilities for drawing use case

UML指南An important part of the Unified Modeling Language (UML) is the facilities for drawing use case diagrams. Use cases are used during the analysis phase of a project to identify and partition system functionality. They separate the system into actors and use cases.
https://www.eeworm.com/dl/542/326947.html
下载: 154
查看: 1036

matlab例程 This directory includes matlab interface of the curvelet transform using usfft. Basic functions

This directory includes matlab interface of the curvelet transform using usfft. Basic functions fdct_usfft.m -- forward curvelet transform afdct_usfft.m -- adjoint curvelet transform ifdct_usfft.m -- inverse curvelet transform fdct_usfft_param.m -- returns the location of each curvelet in phase ...
https://www.eeworm.com/dl/665/339988.html
下载: 97
查看: 1059

书籍源码 MATLAB Code for Optimal Quincunx Filter Bank Design Yi Chen July 17, 2006 This file introduces t

MATLAB Code for Optimal Quincunx Filter Bank Design Yi Chen July 17, 2006 This file introduces the MATLAB code that implements the two algorithms (i.e., Algorithms 1 and 2 in [1], or Algorithms 4.1 and 4.2 in [2]) used for the construction of quincunx filter banks with perfect reconstruction, linear ...
https://www.eeworm.com/dl/532/375399.html
下载: 118
查看: 1140

matlab例程 The following is a list of MATLAB codes which includes the radar absorbing material design, the ant

The following is a list of MATLAB codes which includes the radar absorbing material design, the antenna pattern, the observation points generation, and the amplitude error and phase error calculations.
https://www.eeworm.com/dl/665/376687.html
下载: 56
查看: 1078

VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码

DDR SDRAM控制器的VHDL源代码,含详细设计文档。 The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...
https://www.eeworm.com/dl/663/379154.html
下载: 47
查看: 1064