搜索：parallel
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https://www.eeworm.com/dl/920455.html
技术资料
X84041 EEPROM与8051微控制器接口及其演示代码介绍
The X84041 MPS E2 is an attractive alternative to the'add-on' parallel or serial nonvolatile mem
https://www.eeworm.com/dl/945829.html
技术资料
期刊论文：Systolic realisation for 2-D convolution using configurable
·期刊论文：Systolic realisation for 2-D convolution using configurable functional method in VLSI parallel array
https://www.eeworm.com/dl/648/399203.html
单片机开发
This course is about "distributed algorithms".Distributed algorithms include a wide range of paralle
This course is about "distributed algorithms".Distributed algorithms include a wide range of parallel algorithms,which can be classified by a variety of attributes.
https://www.eeworm.com/dl/899540.html
技术资料
PCA9536 4bit I2C bus and SMBus IO port
The PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose parallelInput/Output
https://www.eeworm.com/dl/899399.html
技术资料
PCA9555 16bit I2C-bus and SMBus IO port with interrupt
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Ou
https://www.eeworm.com/dl/899401.html
技术资料
PCA9537 4bit I2C bus and SMBus low power IO port with interrupt and reset
The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallelInput/Out
https://www.eeworm.com/dl/899432.html
技术资料
PCA9538 8bit I2C bus and SMBus low power IO port with interrupt and reset
The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallelInput/Out
https://www.eeworm.com/dl/655/321830.html
微处理器开发
三星公司官方 GIVEIO.SYS源代码下载。 In windows NT/2000/XP, any application can’t access the I/O such as the par
三星公司官方 GIVEIO.SYS源代码下载。
In windows NT/2000/XP, any application can’t access the I/O such as the parallel port. So, GIVEIO.SYS enables
SJF.exe to access the parallel port without any memory fault. In windows 95/98, GIVEIO.SYS isn’t needed.
https://www.eeworm.com/dl/911865.html
技术资料
BingkouCaozhuo
一个并口通信程序，可以分别设置并口的各个位的状态-A parallel port communication program
https://www.eeworm.com/dl/663/292193.html
VHDL/FPGA/Verilog
vhdl编写
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
E ...