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VHDL/FPGA/Verilog Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci
Stereo-Vision circuit description, Aug 2002,
Ahmad Darabiha
This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and
sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the
sub-circuits can be used as smaller benchmarks.
matlab例程 AHP toolbox AHPCALC Perform a complete AHP calculation. AHPHIER One-step hierarchic
AHP toolbox
AHPCALC Perform a complete AHP calculation.
AHPHIER One-step hierarchical assembly of AHP weighting vector.
AHPREORDER Internal reordering function called by AHPCALC.
AHPVECTOR Calculate the AHP ranking or weighting vector from an
AHP reciproal matrix.
...
论文 基于频率插值的4.0kbps 语音编码器的性能和设计（英文）
The 4.0 kbit/s speech codec described in this paper is based on a
Frequency Domain Interpolative (FDI) coding technique, which
belongs to the class of prototype waveform Interpolation (PWI)
coding techniques. The codec also has an integrated voice
activity detector (VAD) and a noise reduction capabi ...