搜索：digital - 虫虫下载站

DSP编程  DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码，是Spectrum Digital, Inc刚开发出来的！ CPLD Firmware Project CPLD Firmware Project (Version 6).

https://www.eeworm.com/dl/516/371662.html

下载: 36

查看: 1040

DSP编程  DM6467_DaVinciHD_EVM原装开发板原理图和使用说明

DM6467_DaVinciHD_EVM原装开发板原理图和使用说明，用cadence打开。TI的开发板制造商Spectrum Digital公司刚设计的。达芬奇的开发资料目前很少的！

https://www.eeworm.com/dl/516/371671.html

下载: 106

查看: 1042

压缩解压  MPEG-2 has 7 distinct parts as well. The first part is the Systems section which defines the contain

MPEG-2 has 7 distinct parts as well. The first part is the Systems section which defines the container format and the Transport Streams that are designed to carry the digital video and audio over ATSC and DVB. The Program Stream defines the container format for lossy compression on optical disks, DV ...

https://www.eeworm.com/dl/617/374564.html

下载: 159

查看: 1035

单片机开发  数字处理与电机控制一、数字处理单元近代科技技术有一个很重要的趋势

数字处理与电机控制一、数字处理单元近代科技技术有一个很重要的趋势，就是数字化，由于微电子技术的快速发展，带动了数字化科技的落实，从最早的4位处理器，到现在各式各样百花齐放的处理器或微控器，进而牵引了诸多数字化的技术与理论，如﹝电机﹞数字控制、数字相机﹝digital camera﹞、数字通讯，汽车工业等，无一 ...

https://www.eeworm.com/dl/648/377961.html

下载: 22

查看: 1043

其他书籍  The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x&#63722 generation of dig

The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x&#63722 generation of digital signal processor (DSP) controllers, are part of the TMS320C2000&#63722 platform of fixed-point DSPs. The 240xA devices offer the enhanced TMS320&#63722 DSP architectural design of the C2xx core CP ...

https://www.eeworm.com/dl/542/378213.html

下载: 135

查看: 1058

VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码

DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...

https://www.eeworm.com/dl/663/379154.html

下载: 47

查看: 1064

VHDL/FPGA/Verilog 《FPGA数字电子系统设计与开发实例导航》的配套光盘

《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design

https://www.eeworm.com/dl/663/402943.html

下载: 130

查看: 1044

DSP编程  This document describes how to switch to and program the unisersal serial bus (USB) analog phase-lo

This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reade ...

https://www.eeworm.com/dl/516/403303.html

下载: 123

查看: 1068

VHDL/FPGA/Verilog The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that c

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such as VHDL and Verilog

https://www.eeworm.com/dl/663/403510.html

下载: 87

查看: 1084

数据结构  This is an implementation of double-array structure for representing trie, as proposed by Junichi A

This is an implementation of double-array structure for representing trie, as proposed by Junichi Aoe [1]. Trie is a kind of digital search tree, an efficient indexing method with O(1) time complexity for searching. Comparably as efficient as hashing, trie also provides flexibility on incremental m ...

https://www.eeworm.com/dl/654/409492.html

下载: 40

查看: 1147

搜索结果

按分类筛选