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技术管理 一篇关于TCP-Vegas的文献:Vegas is an implementation of TCP that achieves between 37 and 71% better throughpu

一篇关于TCP-Vegas的文献:Vegas is an implementation of TCP that achieves between 37 and 71% better throughput on the Internet, with onefifth to one-half the losses, as compared to the implementation of TCP in the Reno distribution of BSD Unix. This paper motivates and describes the three key techniq ...
https://www.eeworm.com/dl/642/364493.html
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压缩解压 Range imaging offers an inexpensive and accurate means for digitizing the shape of three-dimensiona

Range imaging offers an inexpensive and accurate means for digitizing the shape of three-dimensional objects. Because most objects self occlude, no single range image suffices to describe the entire object. We present a method for combining a collection of range images into a single polygonal mesh t ...
https://www.eeworm.com/dl/617/372623.html
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其他行业 There are several problems related to the properties of the triangular mesh representation that des

There are several problems related to the properties of the triangular mesh representation that describes a surface of an object. Sometimes, the surface is represented just as a set of triangles without any other information and the STL file format, which is used for data exchanges, is a typicalexam ...
https://www.eeworm.com/dl/668/372627.html
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软件工程 Design patterns are elegant, adaptable, and reusable solutions to everyday software development prob

Design patterns are elegant, adaptable, and reusable solutions to everyday software development problems. Programmers use design patterns to organize objects in programs, making them easier to write and modify. C# Design Patterns: A Tutorial is a practical guide to writing C# programs using the most ...
https://www.eeworm.com/dl/540/376264.html
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VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码

DDR SDRAM控制器的VHDL源代码,含详细设计文档。 The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...
https://www.eeworm.com/dl/663/379154.html
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DSP编程 Bootloading the TMS320VC5506/C5507/C5509 A digital signal processor (DSP) through the on-chip unive

Bootloading the TMS320VC5506/C5507/C5509 A digital signal processor (DSP) through the on-chip universal serial bus (USB) peripheral is part of the standard bootloader provided on the device. This document describes the procedures for physically connecting the DSP to a USB host, invoking the USB boot ...
https://www.eeworm.com/dl/516/403305.html
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技术管理 The Software Engineering Institute’s (SEI) Capability Maturity Model (CMM) provides a well-known ben

The Software Engineering Institute’s (SEI) Capability Maturity Model (CMM) provides a well-known benchmark of software process maturity. The CMM has become a popular vehicle for assessing the maturity of an organization’s software process in many domains. This white paper describes how the Rationa ...
https://www.eeworm.com/dl/642/409101.html
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软件设计/软件工程 A class--the basic building block of an object-oriented language such as Java--is a template that de

A class--the basic building block of an object-oriented language such as Java--is a template that describes the data and behavior associated with instances of that class. When you instantiate a class you create an object that looks and feels like other instances of the same class. The data associate ...
https://www.eeworm.com/dl/684/412468.html
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其他书籍 iptables is a firewall onlinux operating system iptables has three tables filter mangle NAT and the

iptables is a firewall onlinux operating system iptables has three tables filter mangle NAT and the document describes how to make rules for them
https://www.eeworm.com/dl/542/421228.html
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其他书籍 Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book descr

Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
https://www.eeworm.com/dl/542/423327.html
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