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DSP编程 基于ti tms320c672x下音频开发例子程式
基于ti tms320c672x下音频开发例子程式，包括eq delay chorus等，还包括usb控制
Linux/Unix编程 NIST Net – A Linux-based Network Emulation Tool, It is a raw IP packet filter with many controllable
NIST Net – A Linux-based Network Emulation Tool, It is a raw IP packet filter with many controllable channel parameters such as packet loss ratio, jitter, bandwidth variation, delay, and network buffer size. To simulate different network environments
书籍源码 一定要在TC下运行
一定要在TC下运行，需要包括一些头文件，如graphic.h
要求：画一辆小车不停地水平从屏幕左边运动到右边，随着每一遍运动，小车高度均匀下降，降到最低后返回最高处
相关函数：delay(),kbhit(),lineto(),moveto(),arc(),circle()等。
单片机开发 VC++环境下的延时程序。sleep函数
VC++环境下的延时程序。sleep函数，还有delay函数。
matlab例程 This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for a
This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for algorithms listed in the textbook Global Positioning Systems, Inertial Navigation, and Integration, by M. S. Grewal, Lawrence Weill, and A. P. Andrews, published by John Wiley and Sons, 2000.
Contents: ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码
DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...
书籍源码 A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he
A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he comp en2
sation cur rent int o t he p assive loop f ilte r during t he delay time of t he p hase f requency detect or ( PFD) , a maximum
reduction of t he p hase noise by about 16dB can be achieved. ...
Delphi控件源码 Permits to negotiate of simple form (without code) some of the most utilized combinations of keys i
Permits to negotiate of simple form (without code) some of the most utilized
combinations of keys in the forms. It suffices with freeing the component on
the form and to activate the properties desired segun the behavior that want.
* ENTER to change of field.
* ESC to close the form
* to ...