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VHDL/FPGA/Verilog It contains a vhdl description of the external bus interface unit for 68000 processor. currently onl
It contains a vhdl description of the external bus interface unit for 68000 processor. currently only read and write cycle are supported
技术资料 Sd_sig.vsd
Sd_sig.vsd
Introduction
Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in
DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide
hidden precharge time and the ability to randomly change column ad ...
技术资料 Sd_cnfg.vsd
Sd_cnfg.vsd
Introduction
Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in
DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide
hidden precharge time and the ability to randomly change column a ...
DSP编程 This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo channe
This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo
channels at a sampling frequency of 48 kHz. The
CYCLE register is embedded in the main
program (
process_data.c) to benchmark the time needed to process two FIR fi lters. A
background telemetry channel (B ...
技术资料 AVRtinyX61core
This is a Atmel AVR ATtiny261/461/861 compatible core.
It should be (more or less) fully code compliant, but it is not clock-cycle compliant.
通讯/手机编程 Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c
Turbo Decoder Release 0.3
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
技术资料 抗毁网状WDM网络中的光纤级P-Cycles优化设计
为降低保护切换代价和提高故障恢复时间，提出了以光纤级P-Cycle来实现网络保护；研究了工作路由与光纤级P-Cycle放置联合优化的设计问题，给出了ILP数学模型。为降低计算的复杂度，采用了一种
matlab例程 matlab雨流算法。The rain flow algorithm code has been prepared according to the ASTM standard (Standard p
matlab雨流算法。The rain flow algorithm code has been prepared according to the ASTM standard (Standard practices for cycle counting in fatigue analysis) and optimized considering the calculation time.
DSP编程 This example demonstrates the use of the ADC block and PWM blocks. The generated DSP code produces t
This example demonstrates the use of the ADC block and PWM blocks. The generated DSP code produces the pulse waveform whose duty cycle is changing as the voltage applied to ADC input changes. The waveform period is kept constant.
技术书籍 Atmel产品的资料
■ High Performance, Low Power AVR® 8-Bit Microcontroller
■ Advanced RISC Architecture
–120 Powerful Instructions – Most Single
Clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation