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找到约 1,388 项符合 cPLD 的查询结果

可编程逻辑 FPGA-CPLD芯片设置方法

FPGA-CPLD芯片设置方法
https://www.eeworm.com/dl/kbcluoji/39270.html
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可编程逻辑 FPGA与CPLD的区别概述

FPGA与CPLD区别
https://www.eeworm.com/dl/kbcluoji/39489.html
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可编程逻辑 CPLD最小系统原理图

CPLD最小系统设计
https://www.eeworm.com/dl/kbcluoji/39625.html
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可编程逻辑 cpld开发套件光盘说明

cpld开发套件光盘说明
https://www.eeworm.com/dl/kbcluoji/39702.html
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可编程逻辑 XAPP444 - CPLD配件,技巧和窍门

Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determ ...
https://www.eeworm.com/dl/kbcluoji/40063.html
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可编程逻辑 XAPP105 - CPLD VHDL介绍

This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD ...
https://www.eeworm.com/dl/kbcluoji/40070.html
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可编程逻辑 XAPP380 -利用CoolRunner-II CPLD创建交叉点开关

  This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensit ...
https://www.eeworm.com/dl/kbcluoji/40074.html
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可编程逻辑 WP264-在数字视频应用中使用CPLD

  The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blo ...
https://www.eeworm.com/dl/kbcluoji/40077.html
下载: 178
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可编程逻辑 XAPP944 - 将Xilinx CoolRunner-II CPLD用作数据流开关

  This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” se ...
https://www.eeworm.com/dl/kbcluoji/40092.html
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可编程逻辑 基于CPLD的VHDL语言数字钟(含秒表)设计

利用一块芯片完成除时钟源、按键、扬声器和显示器(数码管)之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短(设计过程中即可实现时序仿真)、调试方便、故障率低、修改升级容易等特点。 本设计采用自顶向下、混合输入方式(原理图输入—顶层文件连接和VH ...
https://www.eeworm.com/dl/kbcluoji/40186.html
下载: 96
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