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VHDL/FPGA/Verilog cordic IC implement for fast cordic calculate. Including test bench. feature: 1. slicon proved.
cordic IC implement for fast cordic calculate.
Including test bench.
feature:
1. slicon proved.
2. support angle recored algorithm.
VHDL/FPGA/Verilog test bench for spi communication
test bench for spi communication
VHDL/FPGA/Verilog TEst bench of an increment date
TEst bench of an increment date
VHDL/FPGA/Verilog Test Bench for an engine code VHDL for CY7C1062AV33
Test Bench for an engine code VHDL for CY7C1062AV33
VHDL/FPGA/Verilog Test bench for CY7C1062AV33
Test bench for CY7C1062AV33
VHDL/FPGA/Verilog Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design docu
Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
其他书籍 怎样编写仿真功能的测试文件（test bench）
怎样编写仿真功能的测试文件（test bench）
单片机编程 基于C8051F060的数据采集存储系统的设计
介绍一种基于C8051F060单片机和NAND Flash的数据采集存储系统，该系统可实现3路信号采样，每路采样率为5KS/s,通过异步串行通信接口实现数据传输。并详细说明系统的软件设计。
Abstract:
 An acquisition and storage system based on C8051F060and NAND Flash is designed in this paper.The system is used to sam ...
教程资料 UART 4 UART参考设计，Xilinx提供VHDL代码
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl
This zip file contains the following folders:
 \vhdl_source  -- Source VHDL files:
     uart.vhd  - top level file
     txmit.vhd - transmit portion of uart
 &nb ...
可编程逻辑 UART 4 UART参考设计，Xilinx提供VHDL代码
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl
This zip file contains the following folders:
 \vhdl_source  -- Source VHDL files:
     uart.vhd  - top level file
     txmit.vhd - transmit portion of uart
 &nb ...