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教程资料  USB接口控制器参考设计,xilinx提供VHDL代码 us

USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ;&nbsp; This program is free software; you can redistribute it and/or modify ;&nbsp; it under the terms of the GNU General Public License as published by ;&nbsp; the Free Software Foundation; either version 2 of the License, or ;&nbsp; ...

https://www.eeworm.com/dl/fpga/doc/32717.html

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教程资料  ref sdr sdram vhdl代码

ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. ...

https://www.eeworm.com/dl/fpga/doc/32718.html

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教程资料  UART 4 UART参考设计，Xilinx提供VHDL代码

UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: &nbsp;\vhdl_source&nbsp;&nbsp;-- Source VHDL files: &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;uart.vhd &nbsp;- top level file &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;txmit.vhd&nbsp;- transmit portion of uart &nbsp;&nb ...

https://www.eeworm.com/dl/fpga/doc/32719.html

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教程资料  各种功能的计数器实例（VHDL源代码）

各种功能的计数器实例（VHDL源代码）:

https://www.eeworm.com/dl/fpga/doc/32720.html

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教程资料  各种功能的计数器实例（VHDL源代码）

各种功能的计数器实例（VHDL源代码）:ENTITY counters IS &nbsp;PORT &nbsp;( &nbsp;&nbsp;d&nbsp;&nbsp;: IN &nbsp;INTEGER RANGE 0 TO 255; &nbsp;&nbsp;clk&nbsp;&nbsp;: IN&nbsp;BIT; &nbsp;&nbsp;clear&nbsp;: IN&nbsp;BIT; &nbsp;&nbsp;ld&nbsp;&nbsp;: IN&nbsp;BIT; &nbsp;&nbsp;enable&nbsp;: IN&nbsp;BI ...

https://www.eeworm.com/dl/fpga/doc/32721.html

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