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VHDL/FPGA/Verilog max+plusII下编成的直流电机控制器vhd
max+plusII下编成的直流电机控制器vhd
VHDL/FPGA/Verilog max+plusII下的各种功能的计数器vhd
max+plusII下的各种功能的计数器vhd
其他 This class implements the same API as the Java 1.3 java.util.TimerTask. * Note that a TimerTask ca
This class implements the same API as the Java 1.3 java.util.TimerTask.
* Note that a TimerTask can only be scheduled on one Timer at a time, but
* that this implementation does not enforce that constraint.
VHDL/FPGA/Verilog /* This program generates the DApkg.vhd file that is used to define * the DA filter core and give
/* This program generates the DApkg.vhd file that is used to define
* the DA filter core and gives its parameters and the contents of the
* Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm
VHDL/FPGA/Verilog <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.
<Floating Point Unit Core>
fpupack.vhd
pre_norm_addsub.vhd
addsub_28.vhd
post_norm_addsub.vhd
pre_norm_mul.vhd
mul_24.vhd
vcom serial_mul.vhd
post_norm_mul.vhd
pre_norm_div.vhd
serial_div.vhd
post_norm_div.vhd
pre_norm_sqrt.vhd
sqrt.vhd
post_norm_sqrt.vhd
comppack.vhd
fpu.vhd
***For simulation **** ...
Java编程 自己写的一个字符替换的Util
自己写的一个字符替换的Util,支持正则表达式!
VHDL/FPGA/Verilog 数字钟的vhd文档
数字钟的vhd文档,个人感觉还是蛮完善的,大家可以下载了一同改进。
VHDL/FPGA/Verilog fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器
fulladder.vhd 一位全加器
adder.vhd 四位全加器
multi4.vhd 四位并行乘法器
VHDL/FPGA/Verilog count16.vhd 16位BCD计数器VHDL源程序
count16.vhd 16位BCD计数器VHDL源程序
VHDL/FPGA/Verilog seven.vhd 七人表决器VHDL源码 七人表决器.doc 程序说明
seven.vhd 七人表决器VHDL源码
七人表决器.doc 程序说明