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VHDL/FPGA/Verilog This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
VHDL/FPGA/Verilog pci pci转local bus总线的应用
pci pci转local bus总线的应用，使用IPcore
alter器件
通讯编程文档 Meter Bus protocol specification
Meter Bus protocol specification
其他 this is a vhdl code for a bus
this is a vhdl code for a bus
软件工程 pci description.the entire details regarding the pci bus
pci description.the entire details regarding the pci bus
文章/文档 doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
VHDL/FPGA/Verilog I2C program (Inter IC bus)
I2C program (Inter IC bus)
Windows CE 嵌入式系統上 常用 Philips developed Inter-IC bus I2C 之介紹
嵌入式系統上 常用 Philips developed Inter-IC bus I2C 之介紹
嵌入式/单片机编程 PLX 公司 PLX9054 pci target controller local bus interface vhdl programe
PLX 公司 PLX9054 pci target controller local bus interface vhdl programe
软件设计/软件工程 SM 系列无线通信模块。SM-43型低功率无线数传模块使用说明书。
SM 系列无线通信模块。SM-43型低功率无线数传模块使用说明书。