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教程资料  WP362-利用设计保存功能实现可重复的结果

&nbsp; 　　FPGA 设计不再像过去一样只是作为&ldquo;胶连逻辑 (Gluelogic)&rdquo;了，由于其复杂度逐年增加，通常还会集成极富挑战性的 IP 核，如 PCI Express&reg; 核等。新型设计中的复杂模块即便不作任何改变也会在满足 QoR(qualityof-result) 要求方面遇到一些困难。保留这些模块的时序非常耗时，既让人感到头疼， ...

https://www.eeworm.com/dl/fpga/doc/32634.html

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教程资料  基于CPLD的QDPSK调制解调电路设计

为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中 ...

https://www.eeworm.com/dl/fpga/doc/32656.html

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无线通信  Rf And Microwave Power Amplifier Design（2005）

The main objective of this book is to present all the relevant informationrequired for RF and micro-wave power amplifier design includingwell-known and novel theoretical approaches and practical design techniquesas well as to suggest optimum design approaches effectively combininganalytical calcul ...

https://www.eeworm.com/dl/510/36010.html

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无线通信  UHF读写器设计中的FM0解码技术

&nbsp; &nbsp;针对UHF读写器设计中，在符合EPC Gen2标准的情况下，对标签返回的高速数据进行正确解码以达到正确读取标签的要求，提出了一种新的在ARM平台下采用边沿捕获统计定时器数判断数据的方法，并对FM0编码进行解码。与传统的使用定时器定时采样高低电平的FM0解码方法相比，该解码方法可以减少定时器定时误差累积的影 ...

https://www.eeworm.com/dl/510/36490.html

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技术书籍  Algorithms(算法概论)pdf

This book evolved over the past ten years from a set of lecture notes developed while teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students&#39; ...

https://www.eeworm.com/dl/537/36842.html

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C/C++语言编程  基于（英蓓特）STM32V100的看门狗程序

This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent ...

https://www.eeworm.com/dl/503/37359.html

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C/C++语言编程  c8051f330 C程序源代码

//------------------------------------------------------------------------------------//此程序为ADC转换程序，可以选择向ADC0BUSY写1或用定时器0,1,2,3作为ADC的启动信号。////------------------------------------------------------------------------------------//头文件定义//-------------------------------- ...

https://www.eeworm.com/dl/503/37370.html

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可编程逻辑  PCB Design Considerations and Guidelines for 0.4mm and 0.5mm WLPs

Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsidera ...

https://www.eeworm.com/dl/kbcluoji/38883.html

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可编程逻辑  XAPP098 - Spartan FPGA低成本、高效率串行配置

This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration ci ...

https://www.eeworm.com/dl/kbcluoji/40059.html

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可编程逻辑  WP362-利用设计保存功能实现可重复的结果

&nbsp; 　　FPGA 设计不再像过去一样只是作为&ldquo;胶连逻辑 (Gluelogic)&rdquo;了，由于其复杂度逐年增加，通常还会集成极富挑战性的 IP 核，如 PCI Express&reg; 核等。新型设计中的复杂模块即便不作任何改变也会在满足 QoR(qualityof-result) 要求方面遇到一些困难。保留这些模块的时序非常耗时，既让人感到头疼， ...

https://www.eeworm.com/dl/kbcluoji/40144.html

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