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VHDL/FPGA/Verilog 数字秒表的设计
数字秒表的设计，reset为归零设置，start为重新计时设置
微处理器开发 D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger Description A 32 byte block from 22
D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger
Description A 32 byte block from 220h-240h is transfered to 240h-260h
using DMA0 in a burst block using software DMAREQ trigger.
After each transfer, source, destination and DMA size are
reset to inital software setting because DMA tran ...
加密解密 CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b
CRC码产生器与校验器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or asynchronous reset
VHDL/FPGA/Verilog The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until ...
Linux/Unix编程 linux下同一个进程中多个定时器实现。简单描述下定时器模块的实现
linux下同一个进程中多个定时器实现。简单描述下定时器模块的实现，有一个manager单例类保存所有CTimer对象，开启一线程运行延迟函数，每次延迟间隔到，扫描保存CTimer的容器，对每个CTimer对象执行减少时间操作，减少到0则执行回调函数。对一次性CTimer，超时则从容器中删除，循环型的将间隔时间重置，不从容器中移除。
CT ...
其他嵌入式/单片机内容 /* 线路图 89C51 T6963C -------- | 8 P1.0-1.7|=========== D0-7
/*
线路图
89C51 T6963C
--------
| 8
P1.0-1.7|=========== D0-7
|
P3.0|----------- /RD
P3.1|----------- /WR
P3.2|----------- C/D
| -- /CE
| |
| ---
P3.3|----------- /RESET
| VCC--- /HALT
--- ...
其他书籍 DESCRIPTION The DCP0105 family is a series of high efficiency, 5V input isolated DC/DC converters.
DESCRIPTION
The DCP0105 family is a series of high efficiency, 5V
input isolated DC/DC converters. In addition to 1W
nominal galvanically isolated output power capability,
the range of DC/DCs are also fully synchronizable.
The devices feature thermal shutdown, and overload
protection is implemented ...
VHDL/FPGA/Verilog 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器
伪随机序列发生器的vhdl算法
设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）
单片机开发 管脚号 管脚名称 LEVER 管脚功能描述 1 VSS 0V 电源地 2 VDD 5.0V 电源电压 3 VEE 5.0V~(-13V) 液晶显示器驱动电压 4 D/I H/L D/I
管脚号 管脚名称 LEVER 管脚功能描述
1 VSS 0V 电源地
2 VDD 5.0V 电源电压
3 VEE 5.0V~(-13V) 液晶显示器驱动电压
4 D/I H/L D/I=“H”,表示DB7~DB0为显示数据
D/I=“L”,表示DB7~DB0为显示指令数据
5 R/W H/L R/W=“H”,E=“H”,数据被读到DB7~DB0
R/W=“L”,E=“H→L”, DB7~DB0的数据被写到IR或DR
6 E H/L 使能 ...
微处理器开发 The MINI2440 is an effecient ARM9 development board with a comprehensive price, it characterizes sim
The MINI2440 is an effecient ARM9 development board with a comprehensive price, it characterizes simple method and high performance-price ratio. Based on the Samsung S3C2440 microprocessor, it embodies professional stable CPU core power source chip and reset chip to ensure the stability of the syste ...