搜索：Primitive
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https://www.eeworm.com/dl/656/427483.html
Java书籍
Use a one-dimensional array of primitive type boolean to represent the seating chart of the plane.
Use a one-dimensional array of primitive type boolean to represent the seating chart of the
plane. Initialize all the elements of the array to false to indicate that all the seats are
empty. As each seat is assigned, set the corresponding elements of the array to true to
indicate ...
https://www.eeworm.com/dl/534/201818.html
其他
This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a
This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a decimal array that can be used within typical .m file coding.
https://www.eeworm.com/dl/928801.html
技术资料
用M39432设计的简单软件驱动器
This document describes the primitive software drivers for use with the M39432. (The M39432 is a sin
https://www.eeworm.com/dl/663/319494.html
VHDL/FPGA/Verilog
vhdl程序 Uncomment the following lines to use the declarations that are provided for instantiating Xi
vhdl程序 Uncomment the following lines to use the declarations that are
provided for instantiating Xilinx primitive components.
https://www.eeworm.com/dl/fpga/doc/32606.html
教程资料
DS306-PPC405 Virtex-4 Wrapper
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
https://www.eeworm.com/dl/kbcluoji/40087.html
可编程逻辑
DS306-PPC405 Virtex-4 Wrapper
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
https://www.eeworm.com/dl/fpga/doc/32595.html
教程资料
XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
 
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togener ...
https://www.eeworm.com/dl/kbcluoji/40096.html
可编程逻辑
XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
 
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togener ...
https://www.eeworm.com/dl/663/193880.html
VHDL/FPGA/Verilog
Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.
Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6 ...
https://www.eeworm.com/dl/619/273303.html
Linux/Unix编程
The main purpose of this project is to add a new scheduling algorithm to GeekOS and to implement a s
The main purpose of this project is to add a new scheduling algorithm to GeekOS and to implement a simple synchronization primitive (semaphore). As you might have already noticed, GeekOS uses a simple priority based preemptive Round Robin algorithm. In this project, you will chan ...