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同步技术是跳频通信系统的关键技术之一，尤其是在快速跳频通信系统中，常规跳频通信通过同步字头携带相关码的方法来实现同步，但对于快跳频来说，由于是一跳或者多跳传输一个调制符号，难以携带相关码。对此引入双跳频图案方法，提出了一种适用于快速跳频通信系统的同步方案。采用短码携带同步信息，克服了快速跳频难以携带 ...

The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, in ...

Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.

ARM通讯 　　H-JTAG 是一款简单易用的的调试代理软件，功能和流行的MULTI-ICE 类似。H-JTAG 包括两个工具软件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 实现调试代理的功能，而H-FLASHER则实现了FLASH 烧写的功能。H-JTAG 的基本结构如下图1-1所示。　　H-JTAG支持所有基于ARM7 和ARM9的芯片的调试，并且支持大 ...

MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1 ...

　　IP核生成文件：（Xilinx/Altera 同） 　　IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则asyn_fifo.veo 给出了例化该核方式（或者在 Edit－》Language Template-》COREGEN 中找到verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块 ...

MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1 ...

　　中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html 　　Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture 　 　The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class ...

Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for han ...

  According to CIBC World Markets, Equity Research, theFlat Panel Display (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement ...