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Java编程 In the last three articles, I’ve been walking you through the creation of an end-to-end BlackBerry a
In the last three articles, I’ve been walking you through the creation of an end-to-end BlackBerry application that will serve as a mobile front-end to my Knowledge Base sample web application.
Java编程 What I am trying to introduce here is a full fledged Java Instant messenger, which has all the featu
What I am trying to introduce here is a full fledged Java Instant messenger, which has all the features supplied by commercial messengers like Yahoo or MSN. Although it cannot compared to be in par with those messengers, it is an attempt by me to learn Advanced Java and JNI concepts. The challenges ...
Java编程 一个简单而精彩的java聊天室小程序
一个简单而精彩的java聊天室小程序，用my eclipse5.0写的,有客户端和服务端.
VHDL/FPGA/Verilog it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
VHDL/FPGA/Verilog it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
VHDL/FPGA/Verilog it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
VHDL/FPGA/Verilog it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have
it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
VHDL/FPGA/Verilog it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Java编程 本源码是jsp编写的图书管理系统
本源码是jsp编写的图书管理系统，采用的数据库是my sql，内有使用说明和系统模块介绍
DSP编程 TMS6713b receiving by McBSP & EDMA(with reconfiguration of the port depending on taken given) excuse
TMS6713b receiving by McBSP & EDMA(with reconfiguration of the port depending on taken given) excuse me for my english