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行业发展研究 In this paper, we describe the development of a mobile butterfly-watching learning (BWL) system to
In this paper, we describe the development of a mobile butterfly-watching learning (BWL)
system to realize outdoor independent learning for mobile learners. The mobile butterfly-watching
learning system was designed in a wireless mobile ad-hoc learning environment. This is first result
to provide a ...
Delphi控件源码 VCLSkin™ is a component to create skinnable user interface for Delphi/C++Builder application, I
VCLSkin™ is a component to create skinnable user interface for Delphi/C++Builder application, It is easy to use, just put on component on mainform, Vclskin will skin whole application without source code modification.
嵌入式/单片机编程 This guide describes Freescale’s BeeKit Wireless Connectivity Toolkit configuration tool used for Zi
This guide describes Freescale’s BeeKit Wireless Connectivity Toolkit configuration tool used for ZigBee, 802.15.4, or SMAC application development. The guide describes system requirements, installation, and how to launch BeeKit. The book then guides users through a simple step-by-step process of h ...
Ajax Easy Grid is a JS/PHP tool kit for data linear lists management. It can help you to create quickly
Easy Grid is a JS/PHP tool kit for data linear lists management. It can help you to create quickly
interfaces of table list navigation and modification with AJAX features. High performance of the
Grid is ensured by JSON data format. The Easy Grid includes sorting, filtering, pagination and mouse
...
加密解密 Algorithm Festel. Programs read from file to array byte[]. key block = 64 data block = 128 if use
Algorithm Festel.
Programs read from file to array byte[].
key block = 64
data block = 128 if use classis Festel
data block = 256 if use modification Festel
论文 锂硫电池隔膜
Lithium–sulfur batteries are a promising energy-storage technology due to their relatively low cost and high theoretical energy density. However, one of their major technical problems is the shuttling of soluble polysulfides between electrodes, resulting in rapid capacity fading. Here, we present ...
教程 特别好的教程
特别好的教程特别好的教程
Research progress in synthesis and modification of polylactic acid Research progress in synthesis and modification of polylactic acid
技术资料 IEEE_Verilog_2001
The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing o ...
技术资料 ABB机器人编程手册.pdf
ABB机器人编程手册.pdfAliasIO is used to define a signal of any type with an alias name or to use signals in builtin task modules.
Signals with alias names can be used for predefined generic programs, without any
modification of the program before running in different robot installations.
The instruc ...