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通讯/手机编程 iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control
iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- po ...
单片机开发 * The keyboard is assumed to be a matrix having 4 rows by 6 columns. However, this code works for an
* The keyboard is assumed to be a matrix having 4 rows by 6 columns. However, this code works for any
* matrix arrangements up to an 8 x 8 matrix. By using from one to three of the column inputs, the driver
* can support "SHIFT" keys. These keys are: SHIFT1, SHIFT2 and SHIFT3.
单片机开发 51单片机C语言多种点阵屏驱动程序（开发软件为keil C ---8字点阵屏左移程序
51单片机C语言多种点阵屏驱动程序（开发软件为keil C ---8字点阵屏左移程序，64_16点阵屏驱动程序，上移显示程序，左移显示程序）51 monolithic integrated circuit C language many kinds of lattice screen driver (develops the software is keil C ---8 character lattice screen left shift procedure, the 64_16 latt ...
matlab例程 PRINCIPLE: The UVE algorithm detects and eliminates from a PLS model (including from 1 to A componen
PRINCIPLE: The UVE algorithm detects and eliminates from a PLS model (including from 1 to A components) those variables that do not carry any relevant information to model Y. The criterion used to trace the un-informative variables is the reliability of the regression coefficients: c_j=mean(b_j)/std ...
VHDL/FPGA/Verilog The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until ...
单片机开发 M16C/6S 群是采用64 管脚的塑模LQFP 封装的单片机。该群将电力线通信调制解调器内核（利用了Yitran Communications Ltd公司开发的IT800PLC调制解调器技术）和模
M16C/6S 群是采用64 管脚的塑模LQFP 封装的单片机。该群将电力线通信调制解调器内核（利用了Yitran
Communications Ltd公司开发的IT800PLC调制解调器技术）和模拟前端进行了单芯片化。M16C/60系列CPU内
核实现了高级别的编码效率和高速运算处理，而且，内置的IT800调制解调器内核还采用了Yitran公司的DCSK
（Differential C ...
VHDL/FPGA/Verilog DDR SDRAM控制器的VHDL源代码
DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O&#8482 features in the Virtex&#8482 -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...
人工智能/神经网络 neural network utility is a Neural Networks library for the C++ Programmer. It is entirely object o
neural network utility is a Neural Networks library for the
C++ Programmer. It is entirely object oriented and focuses
on reducing tedious and confusing problems of programming neural networks.
By this I mean that network layers are easily defined. An
entire multi-layer network can be created in a f ...
GPS编程 GPS 接收程序 DEMO。 HsGpsDll Library 1.1 A GPS Control/Component for C/C++ HsGpsDll is a Windows Dyn
GPS 接收程序 DEMO。
HsGpsDll Library 1.1
A GPS Control/Component for C/C++
HsGpsDll is a Windows Dynamic Link Library which provides access to any NMEA-183 compliant GPS receiver via a serial communications port. HsGpsDll is designed for use from Visual C, Visual Basic or other languages, capable o ...