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https://www.eeworm.com/dl/534/199176.html 其他

嵌入式文档：Xilinx EDK 实验教程1： Simple Hardware Design

嵌入式文档：Xilinx EDK 实验教程1： Simple Hardware Design
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https://www.eeworm.com/dl/687/202430.html 其他嵌入式/单片机内容

This lab exercise will cover the use of AccelDSP’s design exploration capabilities that include mapp

This lab exercise will cover the use of AccelDSP’s design exploration capabilities that include mapping variables to memory and unrolling loop and vector operations. You will learn how to create different hardware architectures without modifying the MATLAB source to explore diff ...
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https://www.eeworm.com/dl/534/202663.html 其他

The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services.

The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals: To support massive concurrency, on the order of tens of thousands of clients per node To exhibit robust performance under wide variations in load an ...
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https://www.eeworm.com/dl/cadence/ebook/355777.html 电子书籍

This paper provides a rigorous comprehensive approach to the design of the principal software algor

This paper provides a rigorous comprehensive approach to the design of the principal software algorithmsutilized inmodern-day strapdown inertial navigationsystems: integration of angular rate into attitude, acceleration transformation/integration into velocity, and integration of ...
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https://www.eeworm.com/dl/850674.html 技术资料

开关电源的优化设计《Optimal design of switching power supply》

《Optimal design of switching power supply》-Zhanyou Sha-John Wiley and Sons-2015
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https://www.eeworm.com/dl/686/308805.html VC书籍

Design and test a category called Rectangle rectangular, rectangular attribute to the lower left cor

Design and test a category called Rectangle rectangular, rectangular attribute to the lower left corner of the upper-right corner and the coordinates of two points, to calculate the size of rectangular
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https://www.eeworm.com/dl/542/405723.html 其他书籍

Learn about the design tradeoffs involved in creating Windows CE .NET operating system (OS) solution

Learn about the design tradeoffs involved in creating Windows CE .NET operating system (OS) solutions for hardware that implements one of many nonvolatile storage technologies. Different storage technologies, such as NAND and NOR flash memory, masked ROM, and electromechanical Ad ...
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https://www.eeworm.com/dl/663/416926.html VHDL/FPGA/Verilog

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as sma ...
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https://www.eeworm.com/dl/542/423327.html 其他书籍

Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book descr

Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. ...
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https://www.eeworm.com/dl/648/426562.html 单片机开发

定时/计数器PWM设计要点 Timer / Counter PWM design features

定时/计数器PWM设计要点 Timer / Counter PWM design features
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