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文章/文档 ieee投稿须知
ieee投稿须知，The IEEE Transactions on Information Technology in Biomedicine publishes high
quality applications & infrastructure papers that reflect global information technology
advances in medicine and biology and will further address the implementation and management of the broad spectrum of hea ...
VHDL/FPGA/Verilog ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbon
---- ----
---- WISHBONE Wishbone_BFM IP Core ----
---- ----
---- This file is part of the Wishbone_BFM project ----
---- http://www.opencores.org/cores/Wishbone_BFM/ ----
---- ----
---- Description ----
---- Implementation of Wishbone_BFM IP core according to ----
---- Wishbone_BFM IP core specifica ...
其他书籍 Some Aspects of Chess Programming
Some Aspects of Chess Programming，老外写的关于棋类人工智能程序设计的书。
1.overall look on chess programming
2.typical structure of a chess program
3.implementation of my own chess program
4.experiments
系统设计方案 Multirate filters provide a practical approach to designing and implementing finite response (FIR) f
Multirate filters provide a practical approach to designing and implementing finite response (FIR) filters with narrow spectral constraints. By changing the input data rate at one or more intermediate points the filter lengths and computational rates can be greatly reduced when compared to a standar ...
单片机编程 TPS65930 TPS65920与OMAP3530硬件连接
This document describes the system hardware implementation for the OMAP3530 processor and theTPS65930/20 companion power integrated circuit (IC). The document concentrates on the powerconnectivity for the processor and the companion power IC. The document also briefly explains someother specifics re ...
教程资料 WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案：
High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
可编程逻辑 WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案：
High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
文章/文档 This Document provides the High Level Design specification for the Bootloader development and librar
This Document provides the High Level Design specification for the Bootloader development and library porting for ADSP-BF533 based EZ-Kit Lite Board and STAMP Board. This document is meant to be the one of the inputs for the System Test Plan and the overall implementation of the same. This document ...
软件设计/软件工程 ImpulseC Codeveloper fft code. This file implements the hardware portion of a 256 sample FFT using a
ImpulseC Codeveloper fft code. This file implements the hardware portion of a 256 sample FFT using a radix-4 algorithm. This implementation demonstrates that results similar to hand-coded HDL can be achieved
using the C language, and without using a low-level style of C code.
VHDL/FPGA/Verilog Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process
Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality o ...