搜索：Hardware Development

This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outp ...

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Compressor Hardware Baseline features

嵌入式综合  ARM Development Studio5入门教程

arm ds5 教程

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Development Studio5 ARM 入门教程

嵌入式综合  ARM Embedded Development_FSL Kinetis L Series

ARM is the world’s leading semiconductor IP company with 22 Million processors entering the market each day.

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Development_FSL Embedded Kinetis Series

数值算法/人工智能  3D Math Primer for Graphics and Game Development

3D Math Primer for Graphics and Game Development

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Development Graphics Primer Math

电子书籍  aw - test-driven development by example.rar

aw - test-driven development by example.rar

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test-driven development example

电子书籍  Addison.Wesley.Test-Driven.Development.By.Example.chm

Addison.Wesley.Test-Driven.Development.By.Example.chm

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Test-Driven Development Addison Example

其他书籍  Prentice.Java.Oracle.Database.Development.eBook-LiB

Prentice.Java.Oracle.Database.Development.eBook-LiB

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Development eBook-LiB Prentice Database

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嵌入式/单片机编程  Telit GSM module GE863-PRO Hardware User Guide in English

VHDL/FPGA/Verilog Hardware UDP, implementation of UDP based on Altera DE2 using Verilog

VHDL/FPGA/Verilog The Design and Implementation of a Hardware Accelerated Raytracer Using the TM3a FPGA Prototyping

VHDL/FPGA/Verilog This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with