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matlab例程 求取系统的绝对幅度响应、相对的db值幅度响应、相位响应和群延时响应的函数 ％ ％db为相对振幅(dB) ％mag为绝对振幅 ％pha为相位响应 ％grd为群延时 ％w为频率样本点向量 ％
求取系统的绝对幅度响应、相对的db值幅度响应、相位响应和群延时响应的函数
％
％db为相对振幅(dB)
％mag为绝对振幅
％pha为相位响应
％grd为群延时
％w为频率样本点向量
％b为Ha(z)分子多项式系数(对FIR而言，b=h)
％a为Hz(z)分母多项式系数(对FIR而言，a=1)
％ ...
其他 LCDHZ系列13264testlcdC
LCD\HZ系列\13264testlcdC
通讯/手机编程 design LP,HP,B S digital Butterworth and Chebyshev filter. All array has been specified internally
design LP,HP,B S digital Butterworth and Chebyshev
filter. All array has been specified internally,so user only need to
input f1,f2,f3,f4,fs(in hz), alpha1,alpha2(in db) and iband (to specify
the type of to design). This program output hk(z)=bk(z)/ak(z),k=1,2,...,
ksection and the freq.
邮电通讯系统 This program simulates the bit-error-rate (BER) performance of OSTBC with L=4 antennas over the fr
This program simulates the bit-error-rate (BER) performance of OSTBC
with L=4 antennas over the frequency flat Rayleigh block fading channel
The code is developed for real orthogonal design, code rate 1/2
modulation- 16 QAM with gray coding resulting in 2 bits/sec/Hz.
其他书籍 Full compliance with the USB Specification v1.1 and USB CDC v1.1 Support the RS232 Serial interfa
Full compliance with the USB Specification v1.1 and USB CDC v1.1
Support the RS232 Serial interface
Support automatic handshake mode
Support Remote wake-up and power management
256 bytes buffer each for upstream and downstream data flow
Support default ROM or external EEPROM for device configur ...
VHDL/FPGA/Verilog verilog设计的4位频率计
verilog设计的4位频率计，可以测量方波、三角波、正弦波；测量范围10Hz～10MHz，测量分辨率1Hz，测量误差1 Hz；测量通道灵敏度50mv
VHDL/FPGA/Verilog ALTERA上DE2平台
ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。
单片机开发 I often need a simple function generator. Just to generate a certain frequency. After all the years
I often need a simple function generator. Just to generate a certain frequency. After all the years I ve worked with electronics, I still haven t got me one. Even though I need it now and then, I just couldn t seem to justify the cost of one.
So, standard solution - build one yourself.
I designed a ...