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游戏 matematic game design by yunif4 and bayu h
matematic game design by yunif4 and bayu h
VC书籍 本源码是基于C语言的H.264标准的JM源代码模型
本源码是基于C语言的H.264标准的JM源代码模型，附使用说明及相关资料，对于学习H.264标准很有帮助
压缩解压 H.264标准解码器全部verilog源码
H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块
软件设计/软件工程 顺序栈的出栈、入栈、求栈长等基本操作 #include <stdio.h> #include <stdlib.h> #define STACKSIZE 50 typed
顺序栈的出栈、入栈、求栈长等基本操作
#include <stdio.h>
#include <stdlib.h>
#define STACKSIZE 50
typedef char DateType
typedef struct
微处理器开发 ARM的调试下载工具H-JTAG V0.9.0
ARM的调试下载工具H-JTAG V0.9.0，H-JTAG是一款简单易用的的调试代理软件，包括两个工具软件：H-JTAG SERVER和 H-FLASHER。其中，H-JTAG SERVER实现调试代理的功能，而 H-FLASHER则实现了 FLASH烧写的功能。
通讯/手机编程 Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read a
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-p ...
VHDL/FPGA/Verilog This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
其他 寻库小车程发动机h桥测试灯循迹等
寻库小车程发动机h桥测试灯循迹等，图和源程序可供大家参考学习，不错的资料，难得的
Linux/Unix编程 UNIX下编程实现带参数的简单shell.包含1.c、apue.h、error2e.c
UNIX下编程实现带参数的简单shell.包含1.c、apue.h、error2e.c
Linux/Unix编程 UNIX下编程同步与异步write的效率比较。包含apue.h、error2e.c、write.c
UNIX下编程同步与异步write的效率比较。包含apue.h、error2e.c、write.c