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软件设计/软件工程 MISRA-C:2004 Coding Standard The LDRA tool suite is developed and certified to BS EN ISO 9001:2000.
MISRA-C:2004 Coding Standard
The LDRA tool suite is developed and certified to BS EN ISO 9001:2000. This comparison has used the revised MISRA
standard, MISRA-C:2004 "Guidelines for the use of the C language in critical systems" was published in October 2004.
可编程逻辑 使用Nios II紧耦合存储器教程
             使用Nios II紧耦合存储器教程
Chapter 1. Using Tightly Coupled Memory with the Nios II Processor
Reasons for Using Tightly Coupled Memory  . . . . . . . . . . . . . . . . . . . . . . . 1–1
Tradeoffs  . . . . . . . ...
其他书籍 This document discusses recommended practices and style for programmers using the C language in the
This document discusses recommended practices and style for programmers using the C language in the Flight Dynamics Division environment. Guidelines are based on
generally recommended software engineering techniques, industry resources, and local
convention. The Guide offers preferred solutions to c ...
技术资料 DDR3 layout指导
This document provides general hardware and layoutconsiderations and guidelines for hardware engineersimplementing a DDR3 memory subsystem.The rules and recommendations in this document serve as aninitial baseline for board designers to begin their specificimplementations, such as fly-by memory topo ...
allegro Verilog编码中的非阻塞性赋值
 
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
传感与控制 MEMS惯性传感器的焊接指南
Abstract: Standard PCB design and mounting processes can adversely influence MEMS inertial sensors.This application note contains guidelines for the layout, soldering, and mounting of MEMS inertialsensors in LGA packages in order to reduce stresses and improve functionality.
可编程逻辑 Verilog编码中的非阻塞性赋值
 
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
allegro Verilog Coding Style for Efficient Digital Design
 
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
可编程逻辑 Verilog Coding Style for Efficient Digital Design
 
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
Java编程 Thinking in Java, 3rd ed. Revision 4.0 Preface Introduction 1: Introduction to Objects 2
Thinking in Java, 3rd ed. Revision 4.0
Preface
Introduction
1: Introduction to Objects
2: Everything is an Object
3: Controlling Program Flow
4: Initialization & Cleanup
5: Hiding the Implementation
6: Reusing Classes
7: Polymorphism
8: Interfaces & Inner Classes
9: Error Handling with Ex ...