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找到约 155 项符合 Finite-Difference 的查询结果

其他 How to infer a finite state machine for fpga altera xilinx

How to infer a finite state machine for fpga altera xilinx
https://www.eeworm.com/dl/534/421049.html
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数学计算 finite element mesh 参数化有限元网格划分

finite element mesh 参数化有限元网格划分
https://www.eeworm.com/dl/641/423262.html
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数学计算 finite element reduced basis 有限元缩减基源程序

finite element reduced basis 有限元缩减基源程序
https://www.eeworm.com/dl/641/423293.html
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编译器/解释器 very useful for the whom uses finite state machine and it is used for speech

very useful for the whom uses finite state machine and it is used for speech
https://www.eeworm.com/dl/628/429212.html
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matlab例程 matlab工具箱,使用有限元计算ODEs(常微分), PDEs(偏微分),BVPs(边值问题),包括一维,二维,三维.(Matlab Finite Element toolbox,version2.

matlab工具箱,使用有限元计算ODEs(常微分), PDEs(偏微分),BVPs(边值问题),包括一维,二维,三维.(Matlab Finite Element toolbox,version2.01)
https://www.eeworm.com/dl/665/430307.html
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软件设计/软件工程 gaussel code for finite element analysis.for matrix calculation

gaussel code for finite element analysis.for matrix calculation
https://www.eeworm.com/dl/684/439507.html
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文件格式 This file describes the basics of FAT file system. The basic difference between FAT12, Fat16 and FAT

This file describes the basics of FAT file system. The basic difference between FAT12, Fat16 and FAT32 is also protrayed.
https://www.eeworm.com/dl/639/444867.html
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matlab例程 FFTGUI Demonstration of Finite Fourier Transform. FFTGUI(y) plots real(y), imag(y), real(fft(y)

FFTGUI Demonstration of Finite Fourier Transform. FFTGUI(y) plots real(y), imag(y), real(fft(y)) and imag(fft(y)). FFTGUI, without any arguments, uses y = zeros(1,32). When any point is moved with the mouse, the other plots respond. Inspired by Java applet by Dave Hale, Stanford Explo ...
https://www.eeworm.com/dl/665/449126.html
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压缩解压 Adaptive Difference PCM code in matlab

Adaptive Difference PCM code in matlab
https://www.eeworm.com/dl/617/459585.html
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VHDL/FPGA/Verilog Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. T

Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world exam ...
https://www.eeworm.com/dl/663/461363.html
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