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Finite-Difference 的查询结果
模拟电子 DAC技术用语 (D/A Converters Defini
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codec ...
模拟电子 ADC转换器技术用语 (A/D Converter Defi
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relati ...
模拟电子 相敏检波电路鉴相特性的仿真研究
分析了调幅信号和载波信号之间的相位差与调制信号的极性的对应关系,得出了相敏检波电路输出电压的极性与调制信号的极性有对应关系的结论。为了验证相敏检波电路的这一特性,给出3 个电路方案,分别选用理想元件和实际元件,采用Multisim 对其进行仿真实验,直观形象地演示了相敏检波电路的鉴相特性,是传统的实际操作实验所不可 ...
Mentor Design Safe Verilog State Machine（Synplicity）
 
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...
Mentor Creating Safe State Machines(Mentor)
 
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptabl ...
单片机编程 基于单片机89S52的多功能计数器设计
该系统由单片机89S52控制模块，程控宽带放大模块，整形模块，FPGA内频率、相位差测量模块等构成，采用等精度测频法测出频率和周期，可测量有效值为0.01～5V，频率范围1Hz～20MHz信号的频率、周期信号，精度高达10-6。采用计数法测量相位差，该系统可测量有效值0.5～5V，频率10Hz～100kHz信号的相位差，精度为1°。系统功能 ...
单片机编程 基于单片机和FPGA的多功能计数器的设计
以89S52单片机和EP1C6Q240C8型FPGA为控制核心的多功能计数器，是由峰值检波、A/D转换、程控放大、比较整形、移相网络部分组成,可实现测量正弦信号的频率、周期和相位差的功能。多功能计数器采用等精度的测量方法，可实现频率为1Hz～10MHz、幅度为0.01～5Vrms的正弦信号的精确测频，以及频率为10Hz～100kHz、幅度为0.5～5Vrm ...
单片机编程 An easy way to work with Exter
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Requ ...
教程资料 基于CPLD的QDPSK调制解调电路设计
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中 ...
可编程逻辑 Design Safe Verilog State Machine（Synplicity）
 
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...