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测试测量 微电脑型单相交流集合式电表（单相二线系统）
微电脑型单相交流集合式电表（单相二线系统） 特点： 精确度0.25%满刻度±1位数 可同时量测与显示交流电压,電流,頻率,瓦特,(功率因數/視在功率) 交流電壓,電流,瓦特皆為真正有效值(TRMS) 交流電流,瓦特之小數點可任意設定 瓦特單位W或KW可任意設定 CT比可任意設定(1至999) 輸入與輸出絕緣耐压 2仟伏特/1分鐘( 突波測 ...
测试测量 集合式直流电能表（小功率的）
集合式直流电能表（小功率的） 特点： 精确度0.05%满刻度±1位数 可同时量测与显示/直流电压/电流/瓦特（千瓦）/瓦特小时（千瓦小时） 电压输入（DC0-99.99V/0-600.0V）自动变档功能 显示范围0-9999(电流/瓦特/千瓦),0至99999999(八位數瓦特小时)可任意规划 数位RS-485 界面 (Optional) 主要规格： 辅助电源消耗功率 ...
编译器/解释器 Full support for extended regular expressions (those with intersection and complement); Support for
Full support for extended regular expressions (those with intersection and complement); Support for some kinds of cycles in grammar; DFA-based operation; Unicode support; C++ only, requires a modern compiler; Lexical analyzers can be configured to get symbols from any input class (built-in support f ...
电子书籍 Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP
Features
&#8226 Compatible with MCS-51&reg Products
&#8226 8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
&#8226 4.0V to 5.5V Operating Range
&#8226 Fully Static Operation: 0 Hz to 33 MHz
&#8226 Three-level Program Memory Lock
&#8226 256 x 8-bit Internal ...
单片机开发 This example program shows how to configure PCA Module 4 as a watchdog timer. In this example, the
This example program shows how to configure PCA Module 4 as a
watchdog timer. In this example, the watchdog is configured to
overflow after 0xFF00 clock cycles.
书籍源码 MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Description Toggle P5.1 u
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK
Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is
set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK.
Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_ ...
VHDL/FPGA/Verilog // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial //
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General ...
通讯/手机编程 The algorith divides rows in to four equal groups. The rows are then used to from a distance graph w
The algorith divides rows in to four equal groups. The rows are then used to from a distance graph which is then transformed into a matrix. girth of eight is maintained by avoiding six-cycles in the graph construction
通讯/手机编程 Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read a
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-p ...
其他 Topics Practices: Programming and Numerical Methods Practice 1: Introduction to C Practice 2
Topics Practices:
Programming and Numerical Methods
Practice 1: Introduction to C
Practice 2: Cycles and functions
First part cycles
Part Two: Roles
Practice 3 - Floating point arithmetic
Practice 4 - Search for roots of functions
Practice 5 - Numerical Integration
Practice 6 - Arrangement ...