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嵌入式Linux graspForth is my humble attempt at a Forth-in-C that has the following goals: GCC ......... to su
graspForth is my humble attempt at a Forth-in-C that has the following goals:
GCC ......... to support all 32-bit micros that GCC cross-compiles to.
Relocatable . to be able to run in-place in either Flash or Ram.
Fast ........ to be "not much" slower than an assembly based native Forth.
Small ... ...
微处理器开发 Samsung s S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontrol
Samsung s S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in
managed communication hubs and routers.
Windows CE The Davicom DM9008A NDIS CE miniport device driver is used to be the network component of the Micr
The Davicom DM9008A NDIS CE miniport device driver is used to be
the network component of the Microsoft WinCE.net enables hardware
containing Davicom s fast ethernet controller DM9008A
其他 Windows下读写硬件的工具. RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driv
Windows下读写硬件的工具.
RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all the computer hardware, including PCI (PCI Express), PCI Index/Data, Memory, M ...
人工智能/神经网络 人工智能中模糊逻辑算法 FuzzyLib 2.0 is a comprehensive C++ Fuzzy Logic library for constructing fuzzy logic sy
人工智能中模糊逻辑算法
FuzzyLib 2.0 is a comprehensive C++ Fuzzy Logic library for constructing fuzzy logic systems with multi-controller support.
It supports all commonly used shape functions and hedges, with full support for the various types of Aggregation, Correlation, Alphacut, Composition, De ...
其他 RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA
RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all the computer hardware, including PCI (PCI Express), PCI Index/Data, Memory, Memory Index/Data, I/O Spa ...
VHDL/FPGA/Verilog RD1006--I2C与存储器的IP 代码及说明文档
RD1006--I2C与存储器的IP
代码及说明文档,lattice提供,I2C Controller for Serial EEPROMs 源代码可用,并且包含tb文件
嵌入式/单片机编程 verilog程序
verilog程序,实现两个16bit数乘法,采用booth算法,基于状态机实现,分层次为datapath和controller两个子模块,testBench测试通过
文章/文档 The cable compensation system is an experiment system that performs simulations of partial or microg
The cable compensation system is an experiment system that performs simulations of partial or microgravity environments on earth. It is a highly nonlinear and complex system.In this paper, a network based on the theory of the Fuzzy Cerebellum Model Articulation Controller(FCMAC) is proposed to contr ...
VHDL/FPGA/Verilog Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.
Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^ ...