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VHDL/FPGA/Verilog Serial UART open source core. The design is engineered for use as a stand alone chip or for use with

Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we nee ...

https://www.eeworm.com/dl/663/414311.html

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微处理器开发  Schematic of the SMDK6400 Evaluation Board for the S3C6400 chip.

Schematic of the SMDK6400 Evaluation Board for the S3C6400 chip.

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Evaluation Schematic the S3C6400

其他书籍  Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book descr

Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.

https://www.eeworm.com/dl/542/423327.html

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Synthesis Advanced Synopsys Compiler

其他嵌入式/单片机内容  Chip type : ATmega16L Program type : Application Clock frequency : 4.000000 M

Chip type : ATmega16L Program type : Application Clock frequency : 4.000000 MHz Memory model : Small External SRAM size : 0 Data Stack size : 256

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type Application frequency 4.000000

通讯编程文档  LPC2378 user guide to program ARM7 chip.This is a basic document

LPC2378 user guide to program ARM7 chip.This is a basic document

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document program guide basic

单片机开发  This is the Ready project caller Id based on the Atmel Chip 8051... PCB layout is also given in this

This is the Ready project caller Id based on the Atmel Chip 8051... PCB layout is also given in this file

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the project caller layout

单片机开发  C++ source code for accesing serial memory chip with atmega16 microcontroler.

C++ source code for accesing serial memory chip with atmega16 microcontroler.

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microcontroler accesing source atmega

VHDL/FPGA/Verilog Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality o ...

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System-on-Chip Microblaze embedded Spartan

技术资料  USB设备芯片型号检测工具,Chip Genius V2.72

USB设备芯片型号检测工具,Chip Genius V2.72

https://www.eeworm.com/dl/910286.html

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Genius Chip 2.72

微处理器开发  The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and ...

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system-on-chip integrated designed reusable

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