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VHDL/FPGA/Verilog RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the
RS_latch using vhdl,
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q.
Normally, in stor ...
学术论文 基于电力电子网络的变流系统研究.rar
电力电子系统的集成化是现今电力电子技术发展的趋势，系统的模块化和标准化技术是目前电力电子领域的重要研究方向。研究基于电力电子网络的变流系统，对复杂电力电子装置的系统级集成具有重要意义，是电力电子系统集成技术的基本组成部分。本文从变流系统的功率流和信息流双重分布性的角度出发。对电力电子系统网络（Power ...
行业应用文档 NE564的应用电路描述
The NE564 contains the functional blocks shown in Figure 1. Inaddition to the normal PLL functio
模拟电子 LT1017：Circuitry for Single Cell Operation
 
Portable, battery-powered operation of electronic apparatushas become increasingly desirable. Medical, remotedata acquisition, power monitoring and other applicationsare good candidates for battery operation. In some circumstances,due to space, power or reliability considerations,it is pr ...
电源技术 Circuitry for Single Cell Operation
 
Portable, battery-powered operation of electronic apparatushas become increasingly desirable. Medical, remotedata acquisition, power monitoring and other applicationsare good candidates for batteryoperation. In some circumstances,due to space, power or reliability considerations,it is pre ...
单片机编程 基于HITAG读写芯片HTRC110的读写设备设计
Designing read/write device (RWD) units for industrial RF-Identification
applications is strongly facilitated by the NXP Semiconductors HITAG
Reader Chip HTRC110. All needed function blocks, like the antenna
driver, modulator demodulator and antenna diagnosis unit, are integrated
in the HTRC11 ...
单片机编程 基于单片机89S52的多功能计数器设计
该系统由单片机89S52控制模块，程控宽带放大模块，整形模块，FPGA内频率、相位差测量模块等构成，采用等精度测频法测出频率和周期，可测量有效值为0.01～5V，频率范围1Hz～20MHz信号的频率、周期信号，精度高达10-6。采用计数法测量相位差，该系统可测量有效值0.5～5V，频率10Hz～100kHz信号的相位差，精度为1°。系统功能 ...
单片机编程 FREERTOS的官方移植文档
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, ...
教程资料 wp379 AXI4即插即用IP
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting ch ...
教程资料 XAPP740利用AXI互联设计高性能视频系统
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
 and
area optimizat ...