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编译器/解释器 encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in
encode.v The encoder
syndrome.v Syndrome generator in decoder
berlekamp.v Berlekamp algorithm in decoder
chien-search.v Chien search and Forney algorithm in decoder
decode.v The top module of the decoder
inverse.v Computes multiplication inverse of an Galois field element
test-bench.v The tes ...
VHDL/FPGA/Verilog HDL实现的DES算法
HDL实现的DES算法，及相关的Test bench激励文件
其他 The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bi
The Hardware folder contains the following files:-
1) Sram_Interface.bit -----------------> Bitstream File
2) Sram_Interface.ucf -----------------> UCF File
3) Sram_Interface.vhd -----------------> Main Entity
4) Sram_Interface_tb.vhd ------------> Test Bench
5) SRAM_RD_WR.vhd ------------> S ...
VHDL/FPGA/Verilog This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because ...
加密解密 基于 xinlinx 写的DES加密算法
基于 xinlinx 写的DES加密算法，内涵test bench，加密解密都有
VHDL/FPGA/Verilog 计数器 锁存器 12位寄存器 带load
计数器
锁存器
12位寄存器
带load，clr等功能的寄存器
双向脚（clocked bidirectional pin）
一个简单的状态机
一个同步状态机
用状态机设计的交通灯控制器
数据接口
一个简单的UART
测试向量（Test Bench）举例：
加法器源程序 相应加法器的测试向量test bench） ...
微处理器开发 作为数字集成电路的硬件工程师
作为数字集成电路的硬件工程师，在做设计的时候，写Test Bench是很重要的，甚至重要过你的一些设计本身，因为它可以确定你的设计是否可用可行，并且能够优化你的设计。
VHDL/FPGA/Verilog The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro
The Synthetic PIC
Verion 1.1
This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.
It is not, and is not intended as, a high fidelity circuit simulation.
This package includes the following files. Note that the license agreement
is stated in the main VHDL file, PICCPU.VHD and com ...
VHDL/FPGA/Verilog Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuff
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel
conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a
simplified UTMI interface. Currently doesn t do any error checking in
the RX section [should probably check for bit unstuffing errors].
Otherwise complete and fully ...