搜索：BE - 虫虫下载站

可编程逻辑  WP328-FPGA的语音数据融合

&nbsp; The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially instal ...

https://www.eeworm.com/dl/kbcluoji/40101.html

下载: 173

查看: 1038

可编程逻辑  XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接&nbsp; The I/Os in Xilinx&reg; 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...

https://www.eeworm.com/dl/kbcluoji/40104.html

下载: 28

查看: 1114

可编程逻辑  基于Xilinx FPGA的双输出DC/DC转换器解决方案

&nbsp; Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The ...

https://www.eeworm.com/dl/kbcluoji/40111.html

下载: 134

查看: 1025

可编程逻辑  Verilog编码中的非阻塞性赋值

&nbsp; One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...

https://www.eeworm.com/dl/kbcluoji/40125.html

下载: 79

查看: 1029

可编程逻辑  PLD对FPGA数据加密

SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others ...

https://www.eeworm.com/dl/kbcluoji/40127.html

下载: 187

查看: 1036

可编程逻辑  Verilog Coding Style for Efficient Digital Design

&nbsp; In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...

https://www.eeworm.com/dl/kbcluoji/40128.html

下载: 54

查看: 1033

可编程逻辑  US Navy VHDL Modelling Guide

&nbsp; This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the deve ...

https://www.eeworm.com/dl/kbcluoji/40131.html

下载: 130

查看: 1037

可编程逻辑  Design Safe Verilog State Machine（Synplicity）

&nbsp; One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...

https://www.eeworm.com/dl/kbcluoji/40146.html

下载: 20

查看: 1216

可编程逻辑  Creating Safe State Machines(Mentor)

&nbsp; Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptabl ...

https://www.eeworm.com/dl/kbcluoji/40149.html

下载: 134

查看: 1031

可编程逻辑  CPLD库指南

Xilinx is disclosing this user guide, manual, release note, and/or specification (the &ldquo;Documentation&rdquo;) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the D ...

https://www.eeworm.com/dl/kbcluoji/40193.html

下载: 62

查看: 1042

搜索结果

按分类筛选