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https://www.eeworm.com/dl/663/273079.html VHDL/FPGA/Verilog

基于VHDL的8位十进制频率计的详细设计。

基于VHDL的8位十进制频率计的详细设计。
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https://www.eeworm.com/dl/534/276835.html 其他

2000XP下F8禁止和启动加速补丁.网吧常用

2000XP下F8禁止和启动加速补丁.网吧常用
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https://www.eeworm.com/dl/663/277077.html VHDL/FPGA/Verilog

8篇测试向量(Test_Bench)和波形产生的例子(VHDL语言

8篇测试向量(Test_Bench)和波形产生的例子(VHDL语言，开发环境：FPGA)
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https://www.eeworm.com/dl/663/277440.html VHDL/FPGA/Verilog

用EPM7032（CPLD）做的２路８位并行输入ＤＡＣ

用EPM7032（CPLD）做的２路８位并行输入ＤＡＣ，带内部环型振荡器（不用外接时钟振荡源）。
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https://www.eeworm.com/dl/681/280947.html Oracle数据库

Oracle C++ libary support Oracle Database 8,9i,10g

Oracle C++ libary support Oracle Database 8,9i,10g
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https://www.eeworm.com/dl/cadence/ebook/286042.html 电子书籍

ITU V.8 规范,高速传真协议握手时需要用到.

ITU V.8 规范,高速传真协议握手时需要用到.
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https://www.eeworm.com/dl/643/286208.html USB编程

MEGA8做的USB下载线, 既有USB 连接法的讲述

MEGA8做的USB下载线, 既有USB 连接法的讲述，又有SPI 通信!
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https://www.eeworm.com/dl/648/287610.html 单片机开发

This will sample all 8 A/D-channels by the continous mode. Each end of conversion will call an inte

This will sample all 8 A/D-channels by the continous mode. Each end of conversion will call an interrupt routine, where the AD-channel is put to Port4[2..0] and the upper nibble of the result is put to Port4[7..4]. Port 4 is connected to the user LEDs of the FlashCan100P Evaluat ...
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https://www.eeworm.com/dl/647/293341.html 嵌入式/单片机编程

C++ GUI Programming with Qt 4一书中的chap8源码

C++ GUI Programming with Qt 4一书中的chap8源码
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https://www.eeworm.com/dl/534/293441.html 其他

written as well. 8.Strong leadership skills to keep the team motivated and focused at all times to

written as well. 8.Strong leadership skills to keep the team motivated and focused at all times to meet customer deliverables. 9. Experience in managing a team of developers as their technical leader Nice to have requirements: Proven experience on Symbian and/Windows mobile, ...
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