mfsm.vhd

来自「NANDFlashController.zip」· VHDL 代码 · 共 824 行 · 第 1/2 页

                 NxST <= Sr_AdL1;
                 else
                 NxST <= Sr_AdL0;
                 end if;
     when Sr_AdL1 =>
                 t_start <= '1';
                 t_cmd <= "001";
                 ADC_sel <= "10"; 
                 AMX_sel <= "01";
                 if (t_done = '1') then
                 NxST <= Sr_AdL2;
                 else
                 NxST <= Sr_AdL1;
                 end if;
     when Sr_AdL2 =>
                 t_start <= '1';
                 t_cmd   <= "001";
                 ADC_sel <= "10";
                 AMX_sel <= "10";
                 if (t_done = '1') then
                 NxST <= Sr_AdL3;
                 else
                 NxST <= Sr_AdL2;
                 end if;
      when Sr_AdL3 =>
                 t_start <= '1';
                 t_cmd   <= "001";
                 ADC_sel <= "10";
                 AMX_sel <= "11";
                 if (t_done = '1') then
                    NxST <= Sr_CmdL2;
                 else
                    NxST <= Sr_AdL3;
                 end if;  
      when Sr_CmdL2 =>
                 cmd_reg <= C3&C0;
                 cmd_reg_we <= '1';
                 NxST <= Sr_CmdL3;
      when Sr_CmdL3 =>
                 t_start <= '1';
                 t_cmd <= "000";
                 if (t_done = '1') then
                    NxST <= Sr_WC0;
                 else
                    NxST <= Sr_CmdL3;
                 end if;
      when Sr_WC0 =>
                 wCntRes <= '1';
                 NxST <= Sr_WC1;
      when Sr_WC1 =>
                 wCntCE <= '1';
                 if (tc8 = '1') then
                 NxST <= Sr_wait;
                 else
                 NxST <= Sr_WC1;
                 end if;
      when Sr_wait =>
                 if (R_nB = '0') then
                     NxST <= Sr_wait;
                 else
                     NxST <= Sr_RPA0;
                 end if;
      when Sr_RPA0 =>
                 t_start <= '1';
                 t_cmd <= "101";
                 BF_we <= '1';
                 if (t_done = '1') then
                    NxST <= Sr_CmdL4;
                    t_cmd <= "000";
                 else
                    NxST <= Sr_RPA0;
                 end if;
      when Sr_CmdL4 =>
                 cmd_reg <= C0&C5;
                 cmd_reg_we <= '1';
                 set835 <= '1';
                 t_cmd <= "000";
                 NxST <= Sr_CmdL5;
      when Sr_CmdL5 => 
                 t_start <= '1';
                 t_cmd   <= "000"; 
                 if (t_done = '1') then
                    NxST <= Sr_AdL4;
                 else
                    NxST <= Sr_CmdL5;
                 end if;
      when Sr_AdL4 =>
                 t_start <= '1';
                 t_cmd   <= "001"; 
                 ADC_sel <= "10";
                 AMX_sel <= "00"; 
                 if (t_done ='1') then
                    NxST <= Sr_AdL5;
                 else
                    NxST <= Sr_AdL4;
                 end if;
      when Sr_AdL5 =>
                 t_start <= '1';
                 t_cmd   <= "001";
                 ADC_sel <= "10"; 
                 AMX_sel <= "01"; 
                 if (t_done = '1') then
                    NxST <= Sr_CmdL6;
                 else
                    NxST <= Sr_AdL5;
                 end if;
      when Sr_CmdL6 =>
                 cmd_reg <= CE&C0;
                 cmd_reg_we <= '1';
                 NxST <= Sr_CmdL7;
      when Sr_CmdL7 =>
                 t_start <= '1';
                 t_cmd <= "000";
                 wCntRes <= '1'; 
                 if (t_done = '1') then
                    NxST <= Sr_RPA1;
                 else
                    NxST <= Sr_CmdL7;
                 end if;
      when Sr_RPA1 =>
                 t_start <= '1';
                 t_cmd <= "100"; 
                 WrECC <= '1';
                 if (t_done = '1') then
                 NxST <= Sr_wait1;
                 t_cmd <= "011";
                 else
                 NxST <= Sr_RPA1;
                 end if;   
      when Sr_wait1 =>
                 WrECC <= '1';
                 NxST <= Sr_wait2;
      when Sr_wait2 =>
                 WrECC <= '1';
                 NxST <= Sr_WC3;
      when Sr_WC3 =>
                 WrECC <= '1';
                 wCntCE <= '1';
                 if (tc4 = '0') then
                     NxST <= Sr_WC3;
                 else
                     NxST <= Sr_Done;
                 end if;
      when Sr_Done =>
                 setDone <= '1';
                 NxST <= Init;
      when Sw_RAR =>
                 RAR_we <= '1';
                 NxST <= Sw_CmdL0;
      when Sw_CmdL0 =>
                 cmd_reg <= C8&C0;
                 cmd_reg_we <= '1';
                 NxST <= Sw_CmdL1;
      when Sw_CmdL1 =>
                 t_start <= '1';
                 t_cmd <=  "000";
                 if (t_done = '1') then
                    NxST <= Sw_AdL0;
                 else
                    NxST <= Sw_CmdL1;
                 end if;
      when Sw_AdL0 =>
                 t_start <= '1';
                 t_cmd   <= "001";
                 ADC_sel <= "10"; 
                 AMX_sel <= "00";
                 if (t_done = '1') then
                     NxST <= Sw_AdL1;
                 else
                     NxST <= Sw_AdL0;
                 end if;
      when Sw_AdL1 =>
                 t_start <= '1';
                 t_cmd   <= "001"; 
                 ADC_sel <= "10";
                 AMX_sel <= "01";
                 if (t_done = '1') then
                    NxST <= Sw_AdL2;
                 else
                    NxST <= Sw_AdL1;
                 end if;
      when Sw_AdL2 =>
                 t_start <= '1';
                 t_cmd   <= "001";
                 ADC_sel <= "10"; 
                 AMX_sel <= "10";
                 if (t_done = '1') then
                    NxST <= Sw_AdL3;
                 else
                    NxST <= Sw_AdL2;
                 end if;
      when Sw_AdL3 =>
                 t_start <= '1';
                 t_cmd   <= "001";
                 ADC_sel <= "10"; 
                 AMX_sel <= "11";
                 if (t_done = '1') then
                    NxST <= Sw_WPA0;
                 else
                    NxST <= Sw_AdL3;
                 end if;
      when Sw_WPA0 =>
                 t_start <= '1';
                 t_cmd   <= "111";
                 ADC_sel <= "00";
                 if (t_done = '1') then
                    NxST <= Sw_CmdL2;
                    t_cmd <= "000";
                  else
                    NxST <= Sw_WPA0;
                  end if;
      when Sw_CmdL2 =>
                 cmd_reg <= C8&C5;
                 cmd_reg_we <= '1';
                 set835     <= '1';
                 t_cmd   <= "000";
                 NxST    <= Sw_CmdL3;
      when Sw_CmdL3 =>
                 t_start <= '1';
                 t_cmd   <= "000";
                 if (t_done = '1') then
                    NxST <= Sw_AdL4;
                 else
                    NxST <= Sw_CmdL3;
                  end if;
      when Sw_AdL4 =>
                 t_start <= '1';
                 t_cmd   <= "001"; 
                 ADC_sel <= "10"; 
                 AMX_sel <= "00";
                 if (t_done = '1') then
                     NxST <= Sw_AdL5;
                 else
                     NxST <= Sw_AdL4;
                 end if;
      when Sw_AdL5 =>
                 t_start <= '1';
                 t_cmd   <= "001"; 
                 ADC_sel <= "10"; 
                 AMX_sel <= "01";
                 if (t_done = '1') then
                    NxST <= Sw_WPA1;
                 else
                    NxST <= Sw_AdL5;
                 end if;
      when Sw_WPA1 =>
                 t_start <= '1';
                 t_cmd   <= "110"; 
                 ADC_sel <= "01";
                 EnEcc   <= '1';  
                 if (t_done = '1') then
                     NxST <= Sw_CmdL4;
                     t_cmd <= "000";
                  else
                     NxST <= Sw_WPA1;
                  end if;
      when Sw_CmdL4 =>
                 cmd_reg <= C1&C0;
                 t_cmd   <= "000";
                 cmd_reg_we <= '1';
                 NxST <= Sw_CmdL5;
      when Sw_CmdL5 =>
                 t_start <= '1';
                 t_cmd   <= "000"; 
                 if (t_done = '1') then
                     NxST <= Sw_WC1;
                 else
                     NxST <= Sw_CmdL5;
                 end if;
      when Sw_WC1 =>
                 wCntRes <= '1';
                 NxST    <= Sw_WC2;
      when Sw_WC2 => 
                 wCntCE <= '1';
                 if (tc8 = '1') then
                    NxST <= Swait3;
                 else
                    NxST <= Sw_WC2;
                 end if;
      when Swait3 =>
                 if (R_nB = '1') then
                     NxST <= Sw_CmdL6;
                 else
                     NxST <= Swait3;
                 end if;
      when Sw_CmdL6 =>
                 cmd_reg <= C7&C0;
                 cmd_reg_we <= '1';
                 NxST <= Sw_CmdL7;
      when Sw_CmdL7 =>
                 t_start <= '1';
                 t_cmd   <= "000"; 
                 if (t_done = '1') then
                     NxST <= Sw_Wait4;
                 else
                     NxST <= Sw_CmdL7;
                 end if;
      when Sw_Wait4 =>
                 NxST <= Sw_Wait5;
      when Sw_Wait5 =>
                 NxST <= Sw_DR1;
      when Sw_DR1 =>
                 t_start <= '1';
                 t_cmd   <= "010";
                 if (t_done = '1') then
                    NxST <= Sw_done;
                 else
                    NxST <= Sw_DR1;
                 end if;
      when Sw_done =>
                 setDone <= '1';
                 NxST    <= Init;
                 if (io_0 = '1') then
                    SetPrErr <= '1';
                 else 
                    SetPrErr <= '0';
                 end if;
      when Srst_RAR =>
                 NxST <= Srst_CmdL0;
      when Srst_CmdL0 =>
                 cmd_reg <= CF&CF;
                 cmd_reg_we <= '1';
                 NxST <= Srst_CmdL1;
      when Srst_CmdL1 =>
                 t_start <= '1';
                 t_cmd   <= "000";
                 if (t_done = '1') then
                    NxST <= Srst_done;
                 else
                    NxST <= Srst_CmdL1;
                 end if;
      when Srst_done =>
                 setDone <= '1';
                 NxST <= Init;
      when Srid_RAR =>
                 RAR_we <= '1'; 
                 NxST <= Srid_CmdL0;
      when Srid_CmdL0 =>
                 cmd_reg <= C9&C0;
                 cmd_reg_we <= '1';
                 NxST <= Srid_CmdL1;
      when Srid_CmdL1 =>
                 t_start <= '1';
                 t_cmd <= "000";
                 if (t_done = '1') then
                    NxST <= Srid_AdL0;
                 else
                    NxST <= Srid_CmdL1;
                 end if;
      when Srid_AdL0 =>
                 t_start <= '1';
                 t_cmd   <= "001";
                 ADC_sel <= "10"; 
                 AMX_sel <= "10";
                 if (t_done = '1') then
                    NxST <= Srid_Wait;
                 else
                    NxST <= Srid_AdL0;
                 end if;
      when Srid_Wait =>
                 wCntRes <= '1';
                 NxST <= Srid_DR1;
      when Srid_DR1 => 
                 t_start <= '1';
                 t_cmd   <= "010";
                 BF_we   <= '1';
                 if (t_done = '1') then
                     NxST <= Srid_DR2;
                 else
                     NxST <= Srid_DR1;
                 end if;
      when Srid_DR2 =>
                 t_start <= '1';
                 t_cmd   <= "010";
                 BF_we   <= '1';
                 if (t_done = '1') then
                     NxST <= Srid_DR3;
                 else
                     NxST <= Srid_DR2;
                 end if;
      when Srid_DR3 =>
                 t_start <= '1';
                 t_cmd   <= "010";
                 BF_we   <= '1';
                 if (t_done =  '1') then
                     NxST <= Srid_DR4;
                 else
                     NxST <= Srid_DR3;
                 end if;
      when Srid_DR4 =>
                 t_start <= '1';
                 t_cmd   <= "010";
                 BF_we   <= '1';
                 if (t_done = '1') then
                     NxST <= Srid_done;
                 else
                     NxST <= Srid_DR4;
                 end if;
      when Srid_done =>
                 setDone <= '1';
                 NxST <= Init;
      when others =>
                 NxST <= Init;
       END CASE;          
       END IF;         
    END PROCESS;

END ARCHITECTURE translated;