mfsm.v

NANDFlashController.zip

      cmd_reg_we <= 1;
      NxST <= Sr_CmdL3;
    end
    Sr_CmdL3:begin
      t_start <= 1;
      t_cmd <= 3'b000;// -- cmd_latch
      if (t_done ==1)
        NxST <= Sr_WC0;
      else
        NxST <= Sr_CmdL3;
    end
    Sr_WC0:begin
      wCntRes <=1;
      NxST <= Sr_WC1;
    end
    Sr_WC1:begin
      wCntCE <= 1;
      if (tc8 ==1)
        NxST <= Sr_wait;
      else
        NxST <= Sr_WC1;
    end 
    Sr_wait:begin
      if (R_nB==0)
        NxST <= Sr_wait;
      else
        NxST <= Sr_RPA0;
    end 
    Sr_RPA0:begin
      t_start <= 1;
      t_cmd <= 3'b101; // data read w tc2048
      BF_we <= 1;
//      wCntCE <=1;    //wait no tRR
//      EnEcc <= 1;  //-- ecc ctrl
      if (t_done==1)begin
        NxST <= Sr_CmdL4;
        t_cmd <= 3'b000;
      end else
        NxST <= Sr_RPA0;
    end       
    Sr_CmdL4:begin
      cmd_reg <= {C0,C5};
      cmd_reg_we <= 1;
      set835 <= 1;
      t_cmd <= 3'b000;
      NxST <= Sr_CmdL5;
    end
    Sr_CmdL5:begin
      t_start <= 1;
      t_cmd <=3'b000; //-- cmd_latch
      if (t_done) 
        NxST <= Sr_AdL4;
      else
        NxST <= Sr_CmdL5;
    end
    Sr_AdL4:begin
      t_start <= 1;
      t_cmd <= 3'b001; //-- ad_latch
      ADC_sel <= 2'b10;// -- addr to out      
      AMX_sel <= 2'b00; //-- ca1
      if (t_done)
        NxST <= Sr_AdL5;
      else
        NxST <= Sr_AdL4;
    end 
    Sr_AdL5:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <=2'b10; //-- addr to out      
      AMX_sel <=2'b01; //-- ca2
      if (t_done)
        NxST <= Sr_CmdL6;
      else
        NxST <= Sr_AdL5;
    end     
    Sr_CmdL6:begin
      cmd_reg <= {CE,C0};
      cmd_reg_we <= 1;
      NxST <= Sr_CmdL7;
    end
    Sr_CmdL7:begin
      t_start <= 1;
      t_cmd <= 3'b000;// -- cmd_latch
      wCntRes <= 1; //-- sector sel count
//      byteSelCntRes <= 1;
      if (t_done)
        NxST <= Sr_RPA1;
      else
        NxST <= Sr_CmdL7;
    end 
    Sr_RPA1:begin
      t_start <= 1;
      t_cmd <=3'b100; //-- data read w tc3 (12 times - 835-840)
//      byteSelCntEn <= 1;
      WrECC <=1;
//      EnEcc <= 1;  //-- ecc ctrl
      if (t_done) begin 
        NxST <= Sr_wait1;
        t_cmd <= 3'b011;
      end else
        NxST <= Sr_RPA1;
   end 
    Sr_wait1:begin
      WrECC <=1;    
      NxST <= Sr_wait2;
    end
    Sr_wait2:begin
      WrECC <= 1;
      NxST <= Sr_WC3;
    end
    Sr_WC3:begin
      WrECC <=1;
      wCntCE <=1;
//      byteSelCntRes <=1;
      if (tc4 ==0)
        NxST <= Sr_WC3;
      else
        NxST <= Sr_Done;
    end 
    Sr_Done:begin
      setDone <=1;
//      SetRBF<=1;
      NxST <= Init;
    end
    Sw_RAR:begin      //-- WPA
      RAR_we <=1; //--strobe the row address from the host
   //   if (TBF==1)
        NxST <= Sw_CmdL0;
  //    else begin
  //      NxST <= Init;
  //      SetBFerr <=1;
  //      setDone <= 1;
  //    end
    end     
    Sw_CmdL0:begin
      cmd_reg <= {C8,C0};//--h80 to flash data out
      cmd_reg_we <= 1;
      NxST <= Sw_CmdL1;
    end
    Sw_CmdL1:begin
      t_start <=1;
      t_cmd <=3'b000;// -- cmd_latch
      if (t_done ==1)
        NxST <= Sw_AdL0;
      else
        NxST <= Sw_CmdL1;
    end       
    Sw_AdL0:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b00;// -- ca1
      if (t_done ==1)
        NxST <= Sw_AdL1;
      else
        NxST <= Sw_AdL0;
    end
    Sw_AdL1:begin
      t_start <=1;
      t_cmd <=3'b001; //-- ad_latch
      ADC_sel <= 2'b10;// -- addr to out      
      AMX_sel <= 2'b01;// -- ca2
      if (t_done ==1)
        NxST <= Sw_AdL2;
      else
        NxST <= Sw_AdL1;
    end 
    Sw_AdL2:begin
      t_start <=1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b10;// -- ra1
      if (t_done ==1)
        NxST <= Sw_AdL3;
      else
        NxST <= Sw_AdL2;
    end
    Sw_AdL3:begin
      t_start<=1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10; //- addr to out      
      AMX_sel <= 2'b11;// -- ra2
      if (t_done ==1)
        NxST <= Sw_WPA0;
      else
        NxST <= Sw_AdL3;
    end 
    Sw_WPA0:begin
      t_start <=1;
      t_cmd <= 3'b111;// -- data write w tc2048
//      wCntCE <= 1;
      ADC_sel <=2'b00;
//      EnEcc <=1;
      if (t_done==1) begin
        NxST <= Sw_CmdL2;
        t_cmd <=3'b000;
      end else
        NxST <= Sw_WPA0;
    end
    Sw_CmdL2:begin
      cmd_reg <= {C8,C5};
      cmd_reg_we <= 1;
      set835 <= 1;
      t_cmd <= 3'b000;
      NxST <= Sw_CmdL3;
    end
    Sw_CmdL3:begin
      t_start <= 1;
      t_cmd <= 3'b000; //-- cmd_latch
      if (t_done)
        NxST <= Sw_AdL4;
      else
        NxST <= Sw_CmdL3;
    end
    Sw_AdL4:begin
      t_start <= 1;
      t_cmd <= 3'b001; //-- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b00;// -- ca1
      if (t_done)
        NxST <= Sw_AdL5;
      else
        NxST <= Sw_AdL4;
    end 
    Sw_AdL5:begin
      t_start <= 1;
      t_cmd <= 3'b001; //-- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b01;// -- ca2
//      byteSelCntRes <= 1;      
      if (t_done)
        NxST <= Sw_WPA1;
      else
        NxST <= Sw_AdL5;
    end       
    Sw_WPA1:begin
      t_start <= 1;
      t_cmd <= 3'b110; //  -- data write w tc3
//      byteSelCntEn <= 1;
      ADC_sel <= 2'b01;//  -- ecc data to out
//      ecc2flash <= 1;
      EnEcc <= 1;  //-- ecc ctrl
      if (t_done) begin
        NxST <= Sw_CmdL4;
        t_cmd <= 3'b000;
      end else
        NxST <= Sw_WPA1;
    end 
    Sw_CmdL4:begin
      cmd_reg <= {C1,C0};
      t_cmd <= 3'b000;
      cmd_reg_we <= 1;
      NxST <= Sw_CmdL5;
    end
    Sw_CmdL5:begin
      t_start <= 1;
      t_cmd <= 3'b000; //-- cmd_latch
      if (t_done ==1)
        NxST <= Sw_WC1;
      else
        NxST <= Sw_CmdL5;
    end
    Sw_WC1:begin
      wCntRes <=1;
      NxST <= Sw_WC2;
    end
    Sw_WC2:begin
      wCntCE <=1;
      if (tc8 ==1)
        NxST <= Swait3;
      else
        NxST <= Sw_WC2;
    end
    Swait3:begin
      if (R_nB ==1)
        NxST <= Sw_CmdL6;
      else
        NxST <= Swait3;
    end
    Sw_CmdL6:begin
      cmd_reg <= {C7,C0};
      cmd_reg_we <= 1;
      NxST <= Sw_CmdL7;
    end
    Sw_CmdL7:begin
      t_start <=1;
      t_cmd <= 3'b000; //-- cmd_latch
      if (t_done ==1)
        NxST <= Sw_Wait4;
      else
        NxST <= Sw_CmdL7;
    end 
    Sw_Wait4:begin
      NxST <= Sw_Wait5;
    end
    Sw_Wait5:begin
      NxST <= Sw_DR1;
    end
    Sw_DR1:begin
      t_start <=1;
      t_cmd <= 3'b010;// -- read status
      if (t_done ==1)
        NxST <= Sw_done;
      else
        NxST <= Sw_DR1;
    end       
    Sw_done:begin
      setDone <= 1;
      NxST <= Init;
      if (io_0 ==1)
        SetPrErr <=1;
      else begin
        SetPrErr <= 0;
 //       ResTBF<= 1;
      end
    end 
    Srst_RAR:begin               
        NxST <= Srst_CmdL0;
    end     
    Srst_CmdL0:begin
      cmd_reg <= {CF,CF};//--hff to flash data out
      cmd_reg_we <= 1;
      NxST <= Srst_CmdL1;
    end
    Srst_CmdL1:begin
      t_start <=1;
      t_cmd <=3'b000;// -- cmd_latch
      if (t_done ==1)
        NxST <= Srst_done;
      else
        NxST <= Srst_CmdL1;
    end 
    Srst_done:begin
      setDone <= 1;
      NxST <= Init;
    end
    Srid_RAR:begin     
      RAR_we <=1; //--strobe the row address from the host
   //   if (TBF==1)
        NxST <= Srid_CmdL0;
  //    else begin
  //      NxST <= Init;
  //      SetBFerr <=1;
  //      setDone <= 1;
  //    end
    end     
    Srid_CmdL0:begin
      cmd_reg <= {C9,C0};//--h90 to flash data out
      cmd_reg_we <= 1;
      NxST <= Srid_CmdL1;
    end
    Srid_CmdL1:begin
      t_start <=1;
      t_cmd <=3'b000;// -- cmd_latch
      if (t_done ==1)
        NxST <= Srid_AdL0;
      else
        NxST <= Srid_CmdL1;
    end       
    Srid_AdL0:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b10;// -- ra1
      if (t_done ==1)
        NxST <= Srid_Wait;
      else
        NxST <= Srid_AdL0;
    end
    Srid_Wait:begin
      wCntRes <=1;
      NxST <= Srid_DR1;
    end
    Srid_DR1:begin
      t_start <=1;
      t_cmd <= 3'b010;// -- read id
      BF_we <= 1;
      if (t_done ==1)
        NxST <= Srid_DR2;
      else
        NxST <= Srid_DR1;
    end   
    Srid_DR2:begin
      t_start <=1;
      t_cmd <= 3'b010;// -- read id
      BF_we <= 1;
      if (t_done ==1)
        NxST <= Srid_DR3;
      else
        NxST <= Srid_DR2;
    end       
    Srid_DR3:begin
      t_start <=1;
      t_cmd <= 3'b010;// -- read id
      BF_we <= 1;
      if (t_done ==1)
        NxST <= Srid_DR4;
      else
        NxST <= Srid_DR3;
    end       
    Srid_DR4:begin
      t_start <=1;
      t_cmd <= 3'b010;// -- read id
      BF_we <= 1;
      if (t_done ==1)
        NxST <= Srid_done;
      else
        NxST <= Srid_DR4;
    end               
    Srid_done:begin
      setDone <= 1;
      NxST <= Init;
    end 
             
    default:begin
      NxST <= Init;
    end
  endcase
 end
endmodule