cputop.v

流水线CPU的Verilog代码.rar

`timescale 1ns/10ps
`define PERIOD 100

module cputop;
	reg clk;
	reg reset;
	
	initial
		begin
			clk = 1;
			
			system_reset;
		end	

	pipelinedCPU CPU_instance(.clk(clk), .reset(reset));
	
	always #(`PERIOD/2) clk = ~ clk;
	
	task system_reset;
		begin
			reset = 0;
			#(`PERIOD * 0.7) reset = 1;
			#(`PERIOD * 1.5) reset = 0;
		end
	endtask
	
//	task test;
//	begin
//		$readmemb ("test.pro", CPU_instance.instruction_fetch_instance.instruction_memory_instance.memory);
//		$display("instruction_memory loaded successfully!");
//	end
//	endtask
	

endmodule