pipelinedcpu.v

流水线CPU的Verilog代码.rar

`timescale 1ns/10ps

module pipelinedCPU(clk, reset);
	input clk;
	input reset;
	
	wire[31:0] instruction1, instruction2;
	wire[33:0] branch_bus1, branch_bus2;
	wire[107:0] instruction_decode_bus1, instruction_decode_bus2;
	wire[75:0] execution_bus1, execution_bus2;
	wire[75:0] memory_bus1, memory_bus2;
	wire[37:0] write_back_bus1, write_back_bus2;
	
	wire[4:0] execution_destination;
	wire[4:0] memory_destination;
	wire[4:0] write_back_destination;
	
	
	
	//以下是一堆寄存器组
	flopr #(32) INSTRUCTION(.clk(clk), .reset(reset), .d(instruction1), .q(instruction2));
	flopr #(34) BRANCH_BUS(.clk(clk), .reset(reset), .d(branch_bus1), .q(branch_bus2));
	flopr #(108) INSTRUCTION_DECODE_BUS(.clk(clk), .reset(reset), .d(instruction_decode_bus1), .q(instruction_decode_bus2));
	flopr #(76) EXECUTION_BUS(.clk(clk), .reset(reset), .d(execution_bus1), .q(execution_bus2));
	flopr #(76) MEMORY_BUS(.clk(clk), .reset(reset), .d( memory_bus1), .q( memory_bus2));
	flopr #(38) WRITE_BACK_BUS(.clk(clk), .reset(reset), .d(write_back_bus1), .q(write_back_bus2));
		
	instruction_fetch    instruction_fetch_instance(.clk(clk), .reset(reset), .instruction(instruction1), .branch_bus(branch_bus2), .execution_destination(execution_destination), .memory_destination(memory_destination), .write_back_destination(write_back_destination));
	
	instruction_decode   instruction_decode_instance(.clk(clk), .reset(reset), .instruction(instruction2), .execution_destination(execution_destination), .memory_destination(memory_destination), .write_back_destination(write_back_destination), .write_back_bus(write_back_bus2), .branch_bus(branch_bus1), .instruction_decode_bus(instruction_decode_bus1));
	
	execution            execution_instance(.clk(clk), .reset(reset), .instruction_decode_bus(instruction_decode_bus2), .execution_bus(execution_bus1), .execution_destination(execution_destination));
	
	memory_access        memory_access_instance(.clk(clk), .reset(reset), .execution_bus(execution_bus2), .memory_bus(memory_bus1), .memory_destination(memory_destination));
	
	write_back           write_back_instance(.clk(clk), .reset(reset), .memory_bus(memory_bus2), .write_back_bus(write_back_bus1), .write_back_destination(write_back_destination));
endmodule