write_back.v

流水线CPU的Verilog代码.rar

`timescale 1ns/10ps

module write_back(clk, reset, memory_bus, write_back_bus, write_back_destination);
	input clk;
	input reset;
	input[75:0] memory_bus;
	output[37:0] write_back_bus;
	output[4:0] write_back_destination;
	
	wire memory_bus_valid;
	wire[5:0] memory_bus_operation;
	wire[4:0] memory_bus_destination;
	wire[31:0] memory_bus_result;
	wire[31:0] memory_bus_memresult;
	
	reg write_back_bus_valid;
	reg[4:0] write_back_bus_destination;
	reg[31:0] write_back_bus_value;
	
	assign memory_bus_valid = memory_bus[75];
	assign memory_bus_operation = memory_bus[74:69];
	assign memory_bus_destination = memory_bus[68:64];
	assign memory_bus_result = memory_bus[63:32];
	assign memory_bus_memresult = memory_bus[31:0];
	
	wire write_back_enable = (memory_bus_operation == 6'b100000 || memory_bus_operation ==6'b100010 || memory_bus_operation == 6'b100100 || memory_bus_operation == 6'b100101 || memory_bus_operation == 6'b101010 ||
	memory_bus_operation == 6'b100011 || memory_bus_operation ==6'b001000 || memory_bus_operation == 6'b001100 || memory_bus_operation == 6'b001101 ) ? 1'b1 : 1'b0;  //add sub and or slt lw addi andi ori

	wire[31:0] write_back_value = (memory_bus_operation == 6'b100011) ? memory_bus_memresult : memory_bus_result;   // 100011 is lw
	
	always @(posedge clk)
		begin
			if(reset || ! memory_bus_valid)
				begin
					write_back_bus_destination <= 5'b00000;
					write_back_bus_valid <= 0;
				end
			else
				begin
					if(write_back_enable)
						begin
							write_back_bus_valid <= 1;
							write_back_bus_destination <= memory_bus_destination;
							write_back_bus_value <= write_back_value;
						end
						else
							write_back_bus_valid <= 0;
				end
		end
	assign write_back_destination = write_back_bus_destination;
	
	assign write_back_bus[37] = write_back_bus_valid;
	assign write_back_bus[36:32] = write_back_bus_destination;
	assign write_back_bus[31:0] = write_back_bus_value;

endmodule