data_memory.v

流水线CPU的Verilog代码.rar

module data_memory(clk, read_addr, out, write_enable, write_addr, write_value);  //it's a ram
	inout clk;
	input[31:0] read_addr;
	output reg[31:0] out;
	input write_enable;
	input[31:0] write_addr;
	input[31:0] write_value;
	
	reg[7:0] ram[8'b11111111-1:0];
	
	always@(posedge clk)
		begin
			out[7:0] <= ram[read_addr];
			out[15:8] <= ram[read_addr + 1];
			out[23:16] <= ram[read_addr + 2];
			out[31:24] <= ram[read_addr + 3];
			
			if(write_enable)
				begin
					{ram[write_addr + 3], ram[write_addr + 2], ram[write_addr + 1], ram[write_addr]} <= write_value;
				end
		end

	
endmodule