register_file.v

流水线CPU的Verilog代码.rar

module register_file(clk, addr1, out1, addr2, out2, write_enable, write_addr, write_value);  //32 general 32-bit registers
	input clk;
	input[4:0] addr1;   //address of 32 registers, 5 bits needed
	output reg[31:0] out1;
	input[4:0] addr2;
	output reg[31:0] out2;
	input write_enable;
	input[4:0] write_addr;
	input[31:0] write_value;
	
	reg[31:0] Reg[31:0]; //32 general 32-bit registers
	
	initial
		begin
			Reg[0] = 32'h00000000;//Reg[0] is always 0
			
			Reg[18] = 32'h00000001;  //for test
			Reg[19] = 32'h00000002;  //for test
		end
	
	always @(posedge clk)   // positive edge, write
		begin
			if(write_enable)
				begin
					Reg[write_addr] <= write_value;
				end
		end
	
	always @(negedge clk) //negitive dege, read
		begin
			out1 <= Reg[addr1];
			out2 <= Reg[addr2];
		end
endmodule