memory_access.v

流水线CPU的Verilog代码.rar

`timescale 1ns/10ps

module memory_access(clk, reset, execution_bus, memory_bus, memory_destination);
	input clk;
	input reset;
	input[75:0] execution_bus;
	output[75:0] memory_bus;
	output[4:0] memory_destination;
	
	wire execution_bus_valid;
	wire[5:0] execution_bus_operation;
	wire[4:0] execution_bus_destination;
	wire[31:0] execution_bus_result;
	wire[31:0] execution_bus_store_value;
	
	reg memory_bus_valid;
	reg[5:0] memory_bus_operation;
	reg[4:0] memory_bus_destination;
	reg[31:0] memory_bus_result;
	reg[31:0] memory_bus_memresult;  //returned value of memory access
	
	assign execution_bus_valid = execution_bus[75];
	assign execution_bus_operation = execution_bus[74:69];
	assign execution_bus_destination = execution_bus[68:64];
	assign execution_bus_result = execution_bus[63:32];
	assign execution_bus_store_value = execution_bus[31:0];
	
	wire mem_write_enable = ((execution_bus_operation == 6'b101011) ? 1'b1 : 1'b0); //sw
	wire[31:0] mem_write_value = mem_write_enable ? execution_bus_store_value : 0;
	
//	wire mem_read_enable = ((execution_bus_operation == 6'b100011) ? 1'b1 : 1'b0);  //lw
	wire[31:0]  mem_read_out;
	
	data_memory data_memory_instance(.clk(clk), .read_addr(execution_bus_result), .out(mem_read_out), .write_enable(mem_write_enable), .write_addr(execution_bus_result), .write_value(mem_write_value));
	
	always @(posedge clk)
		begin
			if(reset || !execution_bus_valid)
				begin
					memory_bus_destination <= 5'b00000;
					memory_bus_valid <= 0;
				end
			else
				begin
					memory_bus_valid <= 1;
					memory_bus_operation <= execution_bus_operation;
					memory_bus_result <= execution_bus_result;
					memory_bus_destination <= execution_bus_destination;

					memory_bus_memresult <= mem_read_out;
				end
			

		end
	
//	always @(posedge clk)
//		if(execution_bus_valid)
//				memory_bus_memresult = mem_read_out;

	assign memory_destination = memory_bus_destination;
	
	assign memory_bus[75] = memory_bus_valid;
	assign memory_bus[74:69] = memory_bus_operation;
	assign memory_bus[68:64] = memory_bus_destination;
	assign memory_bus[63:32] = memory_bus_result;
	assign memory_bus[31:0] = memory_bus_memresult;
	
endmodule