adc_seg8_display.tan.qmsg

VHDLADC数码管动态扫描.rar

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK BCD_DATA\[3\] ADCINT:inst3\|REGL\[7\] 53.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"BCD_DATA\[3\]\" through register \"ADCINT:inst3\|REGL\[7\]\" is 53.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 12.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_89 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 256 -128 40 272 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns ADCINT:inst3\|current_state.state_bit_2 2 REG LC29 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC29; Fanout = 11; REG Node = 'ADCINT:inst3\|current_state.state_bit_2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK ADCINT:inst3|current_state.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns ADCINT:inst3\|REGL\[7\] 3 REG LC48 96 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC48; Fanout = 96; REG Node = 'ADCINT:inst3\|REGL\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[7] } "NODE_NAME" } } { "../ADCINT/ADCINT.vhd" "" { Text "E:/毕设/软件/ADCINT/ADCINT.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[7] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "../ADCINT/ADCINT.vhd" "" { Text "E:/毕设/软件/ADCINT/ADCINT.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "40.000 ns + Longest register pin " "Info: + Longest register to pin delay is 40.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADCINT:inst3\|REGL\[7\] 1 REG LC48 96 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC48; Fanout = 96; REG Node = 'ADCINT:inst3\|REGL\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADCINT:inst3|REGL[7] } "NODE_NAME" } } { "../ADCINT/ADCINT.vhd" "" { Text "E:/毕设/软件/ADCINT/ADCINT.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns TWO_TO_BCD:inst12\|DIVI:inst1\|lpm_divide:lpm_divide_component\|lpm_divide_pgp:auto_generated\|sign_div_unsign_jkh:divider\|alt_u_div_5le:divider\|add_sub_t9c:add_sub_7\|add_sub_cella\[2\]~122 2 COMB SEXP25 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP25; Fanout = 1; COMB Node = 'TWO_TO_BCD:inst12\|DIVI:inst1\|lpm_divide:lpm_divide_component\|lpm_divide_pgp:auto_generated\|sign_div_unsign_jkh:divider\|alt_u_div_5le:divider\|add_sub_t9c:add_sub_7\|add_sub_cella\[2\]~122'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { ADCINT:inst3|REGL[7] TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~122 } "NODE_NAME" } } { "db/add_sub_t9c.tdf" "" { Text "E:/毕设/软件/ADC_SEG8_DISPLAY/db/add_sub_t9c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 16.000 ns TWO_TO_BCD:inst12\|DIVI:inst1\|lpm_divide:lpm_divide_component\|lpm_divide_pgp:auto_generated\|sign_div_unsign_jkh:divider\|alt_u_div_5le:divider\|add_sub_t9c:add_sub_7\|add_sub_cella\[2\]~140 3 COMB LC18 1 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC18; Fanout = 1; COMB Node = 'TWO_TO_BCD:inst12\|DIVI:inst1\|lpm_divide:lpm_divide_component\|lpm_divide_pgp:auto_generated\|sign_div_unsign_jkh:divider\|alt_u_div_5le:divider\|add_sub_t9c:add_sub_7\|add_sub_cella\[2\]~140'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~122 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~140 } "NODE_NAME" } } { "db/add_sub_t9c.tdf" "" { Text "E:/毕设/软件/ADC_SEG8_DISPLAY/db/add_sub_t9c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 18.000 ns TWO_TO_BCD:inst12\|DIVI:inst1\|lpm_divide:lpm_divide_component\|lpm_divide_pgp:auto_generated\|sign_div_unsign_jkh:divider\|alt_u_div_5le:divider\|add_sub_t9c:add_sub_7\|add_sub_cella\[2\]~129 4 COMB LC19 25 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 18.000 ns; Loc. = LC19; Fanout = 25; COMB Node = 'TWO_TO_BCD:inst12\|DIVI:inst1\|lpm_divide:lpm_divide_component\|lpm_divide_pgp:auto_generated\|sign_div_unsign_jkh:divider\|alt_u_div_5le:divider\|add_sub_t9c:add_sub_7\|add_sub_cella\[2\]~129'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~140 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~129 } "NODE_NAME" } } { "db/add_sub_t9c.tdf" "" { Text "E:/毕设/软件/ADC_SEG8_DISPLAY/db/add_sub_t9c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 28.000 ns SEG8_DISPLAY:inst\|Mux26~246 5 COMB SEXP78 2 " "Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 28.000 ns; Loc. = SEXP78; Fanout = 2; COMB Node = 'SEG8_DISPLAY:inst\|Mux26~246'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~129 SEG8_DISPLAY:inst|Mux26~246 } "NODE_NAME" } } { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 34.000 ns SEG8_DISPLAY:inst\|Mux26~272 6 COMB LC66 1 " "Info: 6: + IC(0.000 ns) + CELL(6.000 ns) = 34.000 ns; Loc. = LC66; Fanout = 1; COMB Node = 'SEG8_DISPLAY:inst\|Mux26~272'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { SEG8_DISPLAY:inst|Mux26~246 SEG8_DISPLAY:inst|Mux26~272 } "NODE_NAME" } } { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 36.000 ns SEG8_DISPLAY:inst\|Mux26~263 7 COMB LC67 1 " "Info: 7: + IC(0.000 ns) + CELL(2.000 ns) = 36.000 ns; Loc. = LC67; Fanout = 1; COMB Node = 'SEG8_DISPLAY:inst\|Mux26~263'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { SEG8_DISPLAY:inst|Mux26~272 SEG8_DISPLAY:inst|Mux26~263 } "NODE_NAME" } } { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 40.000 ns BCD_DATA\[3\] 8 PIN PIN_43 0 " "Info: 8: + IC(0.000 ns) + CELL(4.000 ns) = 40.000 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'BCD_DATA\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { SEG8_DISPLAY:inst|Mux26~263 BCD_DATA[3] } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 312 944 1122 328 "BCD_DATA\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "36.000 ns ( 90.00 % ) " "Info: Total cell delay = 36.000 ns ( 90.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 4.000 ns ( 10.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "40.000 ns" { ADCINT:inst3|REGL[7] TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~122 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~140 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~129 SEG8_DISPLAY:inst|Mux26~246 SEG8_DISPLAY:inst|Mux26~272 SEG8_DISPLAY:inst|Mux26~263 BCD_DATA[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "40.000 ns" { ADCINT:inst3|REGL[7] TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~122 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~140 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~129 SEG8_DISPLAY:inst|Mux26~246 SEG8_DISPLAY:inst|Mux26~272 SEG8_DISPLAY:inst|Mux26~263 BCD_DATA[3] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 6.000ns 2.000ns 8.000ns 6.000ns 2.000ns 4.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[7] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "40.000 ns" { ADCINT:inst3|REGL[7] TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~122 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~140 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~129 SEG8_DISPLAY:inst|Mux26~246 SEG8_DISPLAY:inst|Mux26~272 SEG8_DISPLAY:inst|Mux26~263 BCD_DATA[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "40.000 ns" { ADCINT:inst3|REGL[7] TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~122 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~140 TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~129 SEG8_DISPLAY:inst|Mux26~246 SEG8_DISPLAY:inst|Mux26~272 SEG8_DISPLAY:inst|Mux26~263 BCD_DATA[3] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 6.000ns 2.000ns 8.000ns 6.000ns 2.000ns 4.000ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ADCINT:inst3\|REGL\[0\] ADC_D\[0\] CLK 6.000 ns register " "Info: th for register \"ADCINT:inst3\|REGL\[0\]\" (data pin = \"ADC_D\[0\]\", clock pin = \"CLK\") is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 12.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_89 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 256 -128 40 272 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns ADCINT:inst3\|current_state.state_bit_2 2 REG LC29 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC29; Fanout = 11; REG Node = 'ADCINT:inst3\|current_state.state_bit_2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK ADCINT:inst3|current_state.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns ADCINT:inst3\|REGL\[0\] 3 REG LC61 34 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC61; Fanout = 34; REG Node = 'ADCINT:inst3\|REGL\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[0] } "NODE_NAME" } } { "../ADCINT/ADCINT.vhd" "" { Text "E:/毕设/软件/ADCINT/ADCINT.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "../ADCINT/ADCINT.vhd" "" { Text "E:/毕设/软件/ADCINT/ADCINT.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ADC_D\[0\] 1 PIN PIN_73 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_73; Fanout = 1; PIN Node = 'ADC_D\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADC_D[0] } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 216 -128 40 232 "ADC_D\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns ADCINT:inst3\|REGL\[0\] 2 REG LC61 34 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC61; Fanout = 34; REG Node = 'ADCINT:inst3\|REGL\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { ADC_D[0] ADCINT:inst3|REGL[0] } "NODE_NAME" } } { "../ADCINT/ADCINT.vhd" "" { Text "E:/毕设/软件/ADCINT/ADCINT.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { ADC_D[0] ADCINT:inst3|REGL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { ADC_D[0] ADC_D[0]~out ADCINT:inst3|REGL[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out ADCINT:inst3|current_state.state_bit_2 ADCINT:inst3|REGL[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { ADC_D[0] ADCINT:inst3|REGL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { ADC_D[0] ADC_D[0]~out ADCINT:inst3|REGL[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 14 19:34:41 2010 " "Info: Processing ended: Wed Apr 14 19:34:41 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}