prev_cmp_adc_seg8_display.tan.qmsg

VHDLADC数码管动态扫描.rar

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 256 -128 40 272 "CLK" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ADCINT:inst3\|current_state.state_bit_2 " "Info: Detected ripple clock \"ADCINT:inst3\|current_state.state_bit_2\" as buffer" {  } { { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ADCINT:inst3\|current_state.state_bit_2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register SEG8_DISPLAY:inst\|CNT\[0\] register SEG8_DISPLAY:inst\|CNT\[0\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 76.92 MHz between source register \"SEG8_DISPLAY:inst\|CNT\[0\]\" and destination register \"SEG8_DISPLAY:inst\|CNT\[0\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEG8_DISPLAY:inst\|CNT\[0\] 1 REG LC7 101 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst\|CNT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns SEG8_DISPLAY:inst\|CNT\[0\] 2 REG LC7 101 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst\|CNT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { SEG8_DISPLAY:inst|CNT[0] SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 100.00 % ) " "Info: Total cell delay = 8.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { SEG8_DISPLAY:inst|CNT[0] SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { SEG8_DISPLAY:inst|CNT[0] SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns } { 0.000ns 8.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_89 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 256 -128 40 272 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SEG8_DISPLAY:inst\|CNT\[0\] 2 REG LC7 101 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst\|CNT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_89 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 256 -128 40 272 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SEG8_DISPLAY:inst\|CNT\[0\] 2 REG LC7 101 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst\|CNT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "../SEG8_DISPLAY/SEG8_DISPLAY.vhd" "" { Text "E:/毕设/软件/SEG8_DISPLAY/SEG8_DISPLAY.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { SEG8_DISPLAY:inst|CNT[0] SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { SEG8_DISPLAY:inst|CNT[0] SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns } { 0.000ns 8.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK SEG8_DISPLAY:inst|CNT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SEG8_DISPLAY:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "ADCINT:inst3\|current_state.state_bit_0 EOC CLK 11.000 ns register " "Info: tsu for register \"ADCINT:inst3\|current_state.state_bit_0\" (data pin = \"EOC\", clock pin = \"CLK\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns EOC 1 PIN PIN_59 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_59; Fanout = 1; PIN Node = 'EOC'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { EOC } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 296 -128 40 312 "EOC" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns ADCINT:inst3\|current_state.state_bit_0 2 REG LC64 7 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC64; Fanout = 7; REG Node = 'ADCINT:inst3\|current_state.state_bit_0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { EOC ADCINT:inst3|current_state.state_bit_0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { EOC ADCINT:inst3|current_state.state_bit_0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { EOC EOC~out ADCINT:inst3|current_state.state_bit_0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_89 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC_SEG8_DISPLAY.bdf" "" { Schematic "E:/毕设/软件/ADC_SEG8_DISPLAY/ADC_SEG8_DISPLAY.bdf" { { 256 -128 40 272 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns ADCINT:inst3\|current_state.state_bit_0 2 REG LC64 7 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC64; Fanout = 7; REG Node = 'ADCINT:inst3\|current_state.state_bit_0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK ADCINT:inst3|current_state.state_bit_0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK ADCINT:inst3|current_state.state_bit_0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out ADCINT:inst3|current_state.state_bit_0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { EOC ADCINT:inst3|current_state.state_bit_0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { EOC EOC~out ADCINT:inst3|current_state.state_bit_0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK ADCINT:inst3|current_state.state_bit_0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out ADCINT:inst3|current_state.state_bit_0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}